Oh, that makes sense. I was just thinking when are they going to put turbos on their Naturally Aspirated EUV machines. It is good practice to spell out what abbreviations mean when first using them in an article, even if they should be unambiguous to the reader.
Really looking forward seeing devices with TSMC 5nm chip inside : it is kind of a key milestone for humanity to finally have consumer devices (smartphones) available with chips based on 5nm EUV lithography, having 10 of billions of transistors in less than 100mm2 !!!
That's the density of TSMC's 7nm+ node (they mentioned a transistor density ~115 MTr/mm^2, which translates to 11.5 billion transistors per 100 mm^2). TSMC's 5nm node will have a density of at least 180 MTr/mm^2. That is ~18 billion transistors per 100 mm^2, or ~13 billion transistors per 73 mm^2 (the die size of Snapdragon 855).
Hey Ian, judging by the Intel slide's (2018 week # - 2019 week #), don't you think Intel is actually using EUV for 10nm and that's why it took so long to be up and running? Also explains low volume -- If they can't get more machines, then how are they going to increase capacity? Their chart seems to match the failed i3 10nm graphic disabled chip up to current generation.
Also it would be nice to compare this chart to their quarterly earnings where they reference progress on 10nm... I don't have time right now, but im very curious how it would match up with their message to shareholderss.
No they don't. They have zero reasons to use EUV for 10nm "in secret". That makes no business or any other kind of sense, since keeping this hypothesized clandestine EUV use under wraps would only hurt their stock price. On the contrary, if they were already using EUV they would have announced it long ago. They would have been obligated to their shareholders to announce it, to be more precise. This would go far beyond a lie by omission, since they have repeatedly reported that their 10nm node is based on DUV + SAQP (Self Aligned Quad Patterning).
No, Intel did not use EUV in their 10 nm, and that's one reason they had so much trouble with it. If EUV ad been available at their original 10 nm insertion the whole thing would have been easier.
No EUV machines are going to Intel, and their 10nm isn't using EUV.
ASML has limited capacity to make their TwinScan, and currently all of those are going to TSMC and Samsung. And if TSMC were to have 5nm in HVM by H1 2020, you can bet majority of those are going to TSMC.
The cumulative wafer are also deceptive and does not in anyway represent shipment. At 100mm Die size, 2.5M Wafer would have come out to nearly 625M unit.
This meeting would've taken place right near the end of Intel's chart shown there. (Also just re-reading it, the graphics part is funny. They say 2x graphical performance of Ice Lake with ddr-4 4266mhz memory (versus 3733mhz on other tests) compared to old HD graphics at ddr3-1866mhz memory). and compared on a 5c 5thread versus a 2c 4t cpu. Very odd comparison ;) Everyone knows memory bandwidth affects graphics very heavily. and at resolution the cores would affect graphics too
www.theverge [dot] com/2018/10/22/18009784/intel-10nm-chips-canceled-report-comment This would be week 43 2018. Which is right after their huge scheduled downtime and their first uptick in uptime hours close to a 24hour production shift.
techreport[dot]com/news/33947/intel-sees-excellent-q2-2018-results-amidst-news-of-10-nm-delays/ All of these reports, when comparing to this slide, correspond with waiting for EUV machines, and match with their reports about 10nm. Something in 10nm is using EUV that they couldn't do with DUV. and judging by the graph, I bet the big red scheduled downtime before production became 24hour shifts was infact installing a second EUV machine in the line somewhere.
All of the pieces match. Intel's 10nm+ is TSMC's 7nm+ in a sense, EUV layers and DUV layers. Intel's hold back is currently just machines that can produce EUV chips, hence laptop only. I wonder how many machines of EUV intel has, can you find out? Can calculate wafers/hour and match with their 10nm laptop sales. I bet they would match up very closely.
No. Intel is not using EUV, and timing wise, even if they had added EUV to their 10 nm lines it would have had to be after they already had problems with the original 10 nm that was based entirely on DUV. It's hard to know how many EUV machines Intel has, but they would rather be using them for their upcoming 7 nm node, and as someone else pointed out, it doesn't make sense for them to lie about not using EUV on the node.
After all the lying and deceptive marketing towards AMD recently regarding benchmarks and comparisons, your really going to say it doesn't make sense for them to lie about using EUV in their 10nm+ vs their failed 10nm DUV? They are saving face. And also, 14nm++ is extending into 2020 for desktop and server chips. You could argue that once they have enough EUV machines, they will transition directly from 14nm++ to 7nm in those product segments and transition the 10nm+ lines directly to 7nm also. Why make it high volume if your going to basically leapfrop it?
And regarding the latest slide Anandtech showed, with backport capability. 10nm++ to 7nm backport. If you use Ian's logic of each plus basically representing a different node (like 9nm, 8nm), the backporting becomes more logical. Because as they transition to ++ and EUV backward compatibility will be easy. Basically as long as the transitors and gates are at a set percentage throughout the design, they can just scale up design (120% transitor, 140% gate, etc) and make the design backward compatible easily instead of optimizing specifically for each node characteristic to extract maximum performance.
Because as they install the EUV machines, if they are capable of 7nm why wouldn't they be capable of 10nm++? That's why the new strategy exists. The new machines are capable of much more so just making the design bigger if they run into problems is much easier when they are using next-gen technology versus DUV.
Yes, I am going to say that. Because, regardless of what "lying and deceptive marketing towards AMD" you are talking about (why is Intel marketing their products towards AMD?), they would presumably have some reason of doing so. They do not have any reason to lie about using EUV. I don't see why you think a backport will be "easy" to implement if they both use EUV. For example, even if they were to both use EUV they would probably use it for a different number of layers. It just sounds like you are blowing smoke here. I don't think they can "just scale up the design". Laying out a chip is very complicated and the characteristics of the transistors change what the optimal layout is. They need to worry about hotspots. There are different parts of the entire chip assembly, i.e., the beol, feol, etc., that have different purposes. I have no idea what leaving open the option to backport entails, but I am sure you don't either.
Their deceptive marketing towards comparing their products toward AMD's is due to their inefficiency and uncompetitive current lineup. Trying to change which benchmarks are used, co-developing AI-XPRT, and another one i forget, getting user benchmark to change the score weightings to lower AMD's score, recommending people benchmark with tools like matlab (Intel Compiler, cripples AMD to SSE but if you write a batch script to trick the program into thinking its Intel, it will run full speed on AVX.)
Everything Intel does reflects on the company they have become. Why would they admit they failed 10nm and use EUV for 10nm+? It would make them look worse. Especially because their yields on 10nm are very low and they haven't been able to scale it to server and desktop yet, after 5-6 years.
There's alot of reasons to lie. And once they get more EUV machines and work out the kinks for 7nm, they will adjust the 10nm+ line last and just easily convert to 7nm. Simple as that.
And if their transistors placement and gates are a certain percentage different across the entire product (20% smaller, etc), it makes backporting much easier. They can just scale the design and have an engineer rework the circuits for the increased space. Same way Vega was made on 7nm with very little effort for the Radeon VII.
No more specific-characteristic of node optimizations, they are creating a system where everything is relative per node, so designs can be scaled by the relative difference. Yes it's a little more technical than that, but that's basically how it works. When you specifically optimize for specific parts of a node that are design rules that can only benefit the characteristics of that particular node, you have to re-design it for a different node. If you lower the rules and make common rules across nodes, backporting is much easier. You don't have edge-cases that have to be redesigned, everything is compatible. (It also makes it have less performance because of that, but the +'s are specific optimizations.)
I really don't understand what your defending. It's not a fanboy argument, it's the reality of the situation. We can disagree on whether or not EUV is used because they won't disclose it and the people working on it are NDA bound, but if you think about it instead of just dismissing it - it makes alot of sense given the situation they are in.
Enough with your conspiracy theory. There is a 0% chance that Intel was secretly using EUV all along because, as market watchers can easily prove to you, 100% of the NXE3400B scanners were pre-purchased by Samsung and TSMC for 2 consecutive years (2017/2018).
I'm not defending anything. I am questioning why you think Intel would say they are not using EUV on a process node when they in fact are. What would ASML think about that? Obviously ASML knows whether they are or are not doing that. It just wouldn't look good. ASML is a long-term partner. And what's the reason, anyway? What does Intel get out of it? It just makes little sense to me, and you haven't made any argument that provides a reasonable motive for them to do so. As far as I can see, your whole argument is "It would make them look worse." Why would it look worse if they said they used EUV? Do you realize that all these companies participate in industry conferences where they share various data on matters that concern the whole industry. Some of those matters would be necessary developments from other companies in order to make EUV insertion more efficient. If Intel were hiding their true experience with EUV they would not be able to make these observations public, thus shooting themselves in the foot. Just because someone has the opportunity to commit a crime ("they could possibly have the machines") and the character to commit a crime ("Intel has deceptive marketing", doesn't mean it's been committed by them. Without a convincing motive for them to do something weird like hiding the use of EUV it's just nonsense.
Oh look, your the same guy defending Intel on the other article. and yes, they struggled for what? Like 5 years? 10nm completely failed. Only chip to come out was graphic disabled i3. 2 core i think. Now Ice Lake is 10nm+. Which if that chart is accurately representing Ice Lake (which I believe it may be), that means end of 2018 they finally sorted out their issues, which corresponds to them saying that their 10nm is ahead of schedule and doing well. It doesn't show yields but I'm sure that this was what they were referencing when they said ahead of schedule. The uptime.
You obviously have a hatred for Intel, and I think it's clouding your judgment. I have no particular love for Intel. I think the company has become a corporate boondoggle and is wasting a lot of money. But I also see people that seen to resent Intel just because they are big and successful, and those people say things that confirm their biases and wishes without fully considering the situations. As an example, in the other article, where people conveniently show no awareness of the differences between Intel's position and TSMC's that can make a process successful for TSMC which would be a failure for Intel.
As for what you just said, if TSMC can get their 7 nm to work OK without EUV then why can't Intel get their 10 nm to work? They just needed more time. From what I've seen, insertion of EUV in a process is a big deal and it demands a major redesign. Sure it's possible Intel helped their 10 nm problems by using EUV, but why wouldn't they just say that? Anyway, I've had enough of this topic. You can be sure of whatever you want.
3nm will mean whatever TSMC wants it to mean, ie whatever is ready to roll out in 2022. This MAY be smaller lithography (driven by high NA). OR it may mean GAA transistors at 5nm lithography. OR it may mean new materials OR...
That's why TSMC is king: because they're testing multiple things simultaneously, but they only move the non-risky ones into production, AND they don't shoot their mouths off about what they'll be doing ten years from now, so they have no particular stake in what "defines" the 3nm node. 3nm will be exactly what I said -- all the stuff that's ready to roll in 2022, none of the stuff that isn't.
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FreckledTrout - Wednesday, December 11, 2019 - link
Everytime I see High-NA I think of hypernatremia but then I have to remind myself NA is not standing for sodium its numerical aperture.Death666Angel - Wednesday, December 11, 2019 - link
And that's why capitalization is important. :DFreeb!rd - Thursday, December 12, 2019 - link
I thought it meant Highly-NotAvailable... like the Infinite Improbability Drive. ; )https://www.youtube.com/watch?v=UIUIO1ImtJo
katsetus - Thursday, December 12, 2019 - link
Oh, that makes sense. I was just thinking when are they going to put turbos on their Naturally Aspirated EUV machines.It is good practice to spell out what abbreviations mean when first using them in an article, even if they should be unambiguous to the reader.
Diogene7 - Wednesday, December 11, 2019 - link
Really looking forward seeing devices with TSMC 5nm chip inside : it is kind of a key milestone for humanity to finally have consumer devices (smartphones) available with chips based on 5nm EUV lithography, having 10 of billions of transistors in less than 100mm2 !!!Santoval - Wednesday, December 11, 2019 - link
That's the density of TSMC's 7nm+ node (they mentioned a transistor density ~115 MTr/mm^2, which translates to 11.5 billion transistors per 100 mm^2). TSMC's 5nm node will have a density of at least 180 MTr/mm^2. That is ~18 billion transistors per 100 mm^2, or ~13 billion transistors per 73 mm^2 (the die size of Snapdragon 855).Fataliity - Wednesday, December 11, 2019 - link
Hey Ian, judging by the Intel slide's (2018 week # - 2019 week #), don't you think Intel is actually using EUV for 10nm and that's why it took so long to be up and running? Also explains low volume -- If they can't get more machines, then how are they going to increase capacity? Their chart seems to match the failed i3 10nm graphic disabled chip up to current generation.Think about it...
Fataliity - Wednesday, December 11, 2019 - link
Also it would be nice to compare this chart to their quarterly earnings where they reference progress on 10nm... I don't have time right now, but im very curious how it would match up with their message to shareholderss.extide - Wednesday, December 11, 2019 - link
No. It's only in dev.Santoval - Wednesday, December 11, 2019 - link
No they don't. They have zero reasons to use EUV for 10nm "in secret". That makes no business or any other kind of sense, since keeping this hypothesized clandestine EUV use under wraps would only hurt their stock price.On the contrary, if they were already using EUV they would have announced it long ago. They would have been obligated to their shareholders to announce it, to be more precise. This would go far beyond a lie by omission, since they have repeatedly reported that their 10nm node is based on DUV + SAQP (Self Aligned Quad Patterning).
Yojimbo - Wednesday, December 11, 2019 - link
No, Intel did not use EUV in their 10 nm, and that's one reason they had so much trouble with it. If EUV ad been available at their original 10 nm insertion the whole thing would have been easier.ksec - Thursday, December 12, 2019 - link
No EUV machines are going to Intel, and their 10nm isn't using EUV.ASML has limited capacity to make their TwinScan, and currently all of those are going to TSMC and Samsung. And if TSMC were to have 5nm in HVM by H1 2020, you can bet majority of those are going to TSMC.
The cumulative wafer are also deceptive and does not in anyway represent shipment. At 100mm Die size, 2.5M Wafer would have come out to nearly 625M unit.
Speedfriend - Friday, December 13, 2019 - link
Intel definitely has EUV machines, they are using them on 7nm. They funded the development of EUV together with TSMC and SamsungFataliity - Wednesday, December 11, 2019 - link
newsroom.intel [dot] com/news/2019-intel-investor-meeting/This meeting would've taken place right near the end of Intel's chart shown there. (Also just re-reading it, the graphics part is funny. They say 2x graphical performance of Ice Lake with ddr-4 4266mhz memory (versus 3733mhz on other tests) compared to old HD graphics at ddr3-1866mhz memory). and compared on a 5c 5thread versus a 2c 4t cpu. Very odd comparison ;) Everyone knows memory bandwidth affects graphics very heavily. and at resolution the cores would affect graphics too
www.theverge [dot] com/2018/10/22/18009784/intel-10nm-chips-canceled-report-comment
This would be week 43 2018. Which is right after their huge scheduled downtime and their first uptick in uptime hours close to a 24hour production shift.
techreport[dot]com/news/33947/intel-sees-excellent-q2-2018-results-amidst-news-of-10-nm-delays/
All of these reports, when comparing to this slide, correspond with waiting for EUV machines, and match with their reports about 10nm. Something in 10nm is using EUV that they couldn't do with DUV. and judging by the graph, I bet the big red scheduled downtime before production became 24hour shifts was infact installing a second EUV machine in the line somewhere.
All of the pieces match. Intel's 10nm+ is TSMC's 7nm+ in a sense, EUV layers and DUV layers. Intel's hold back is currently just machines that can produce EUV chips, hence laptop only. I wonder how many machines of EUV intel has, can you find out? Can calculate wafers/hour and match with their 10nm laptop sales. I bet they would match up very closely.
Yojimbo - Wednesday, December 11, 2019 - link
No. Intel is not using EUV, and timing wise, even if they had added EUV to their 10 nm lines it would have had to be after they already had problems with the original 10 nm that was based entirely on DUV.It's hard to know how many EUV machines Intel has, but they would rather be using them for their upcoming 7 nm node, and as someone else pointed out, it doesn't make sense for them to lie about not using EUV on the node.
Fataliity - Wednesday, December 11, 2019 - link
After all the lying and deceptive marketing towards AMD recently regarding benchmarks and comparisons, your really going to say it doesn't make sense for them to lie about using EUV in their 10nm+ vs their failed 10nm DUV? They are saving face. And also, 14nm++ is extending into 2020 for desktop and server chips. You could argue that once they have enough EUV machines, they will transition directly from 14nm++ to 7nm in those product segments and transition the 10nm+ lines directly to 7nm also. Why make it high volume if your going to basically leapfrop it?And regarding the latest slide Anandtech showed, with backport capability. 10nm++ to 7nm backport. If you use Ian's logic of each plus basically representing a different node (like 9nm, 8nm), the backporting becomes more logical. Because as they transition to ++ and EUV backward compatibility will be easy. Basically as long as the transitors and gates are at a set percentage throughout the design, they can just scale up design (120% transitor, 140% gate, etc) and make the design backward compatible easily instead of optimizing specifically for each node characteristic to extract maximum performance.
Look at the bigger picture..
Fataliity - Wednesday, December 11, 2019 - link
Because as they install the EUV machines, if they are capable of 7nm why wouldn't they be capable of 10nm++? That's why the new strategy exists. The new machines are capable of much more so just making the design bigger if they run into problems is much easier when they are using next-gen technology versus DUV.Yojimbo - Thursday, December 12, 2019 - link
Yes, I am going to say that. Because, regardless of what "lying and deceptive marketing towards AMD" you are talking about (why is Intel marketing their products towards AMD?), they would presumably have some reason of doing so. They do not have any reason to lie about using EUV. I don't see why you think a backport will be "easy" to implement if they both use EUV. For example, even if they were to both use EUV they would probably use it for a different number of layers. It just sounds like you are blowing smoke here. I don't think they can "just scale up the design". Laying out a chip is very complicated and the characteristics of the transistors change what the optimal layout is. They need to worry about hotspots. There are different parts of the entire chip assembly, i.e., the beol, feol, etc., that have different purposes. I have no idea what leaving open the option to backport entails, but I am sure you don't either.Fataliity - Thursday, December 12, 2019 - link
Their deceptive marketing towards comparing their products toward AMD's is due to their inefficiency and uncompetitive current lineup. Trying to change which benchmarks are used, co-developing AI-XPRT, and another one i forget, getting user benchmark to change the score weightings to lower AMD's score, recommending people benchmark with tools like matlab (Intel Compiler, cripples AMD to SSE but if you write a batch script to trick the program into thinking its Intel, it will run full speed on AVX.)Everything Intel does reflects on the company they have become. Why would they admit they failed 10nm and use EUV for 10nm+? It would make them look worse. Especially because their yields on 10nm are very low and they haven't been able to scale it to server and desktop yet, after 5-6 years.
There's alot of reasons to lie. And once they get more EUV machines and work out the kinks for 7nm, they will adjust the 10nm+ line last and just easily convert to 7nm. Simple as that.
And if their transistors placement and gates are a certain percentage different across the entire product (20% smaller, etc), it makes backporting much easier. They can just scale the design and have an engineer rework the circuits for the increased space. Same way Vega was made on 7nm with very little effort for the Radeon VII.
No more specific-characteristic of node optimizations, they are creating a system where everything is relative per node, so designs can be scaled by the relative difference. Yes it's a little more technical than that, but that's basically how it works. When you specifically optimize for specific parts of a node that are design rules that can only benefit the characteristics of that particular node, you have to re-design it for a different node. If you lower the rules and make common rules across nodes, backporting is much easier. You don't have edge-cases that have to be redesigned, everything is compatible. (It also makes it have less performance because of that, but the +'s are specific optimizations.)
Fataliity - Thursday, December 12, 2019 - link
I really don't understand what your defending. It's not a fanboy argument, it's the reality of the situation. We can disagree on whether or not EUV is used because they won't disclose it and the people working on it are NDA bound, but if you think about it instead of just dismissing it - it makes alot of sense given the situation they are in.FullmetalTitan - Thursday, December 12, 2019 - link
Enough with your conspiracy theory. There is a 0% chance that Intel was secretly using EUV all along because, as market watchers can easily prove to you, 100% of the NXE3400B scanners were pre-purchased by Samsung and TSMC for 2 consecutive years (2017/2018).Yojimbo - Saturday, December 14, 2019 - link
I'm not defending anything. I am questioning why you think Intel would say they are not using EUV on a process node when they in fact are. What would ASML think about that? Obviously ASML knows whether they are or are not doing that. It just wouldn't look good. ASML is a long-term partner. And what's the reason, anyway? What does Intel get out of it? It just makes little sense to me, and you haven't made any argument that provides a reasonable motive for them to do so. As far as I can see, your whole argument is "It would make them look worse." Why would it look worse if they said they used EUV? Do you realize that all these companies participate in industry conferences where they share various data on matters that concern the whole industry. Some of those matters would be necessary developments from other companies in order to make EUV insertion more efficient. If Intel were hiding their true experience with EUV they would not be able to make these observations public, thus shooting themselves in the foot. Just because someone has the opportunity to commit a crime ("they could possibly have the machines") and the character to commit a crime ("Intel has deceptive marketing", doesn't mean it's been committed by them. Without a convincing motive for them to do something weird like hiding the use of EUV it's just nonsense.Fataliity - Wednesday, December 11, 2019 - link
Oh look, your the same guy defending Intel on the other article. and yes, they struggled for what? Like 5 years? 10nm completely failed. Only chip to come out was graphic disabled i3. 2 core i think. Now Ice Lake is 10nm+. Which if that chart is accurately representing Ice Lake (which I believe it may be), that means end of 2018 they finally sorted out their issues, which corresponds to them saying that their 10nm is ahead of schedule and doing well. It doesn't show yields but I'm sure that this was what they were referencing when they said ahead of schedule. The uptime.Yojimbo - Saturday, December 14, 2019 - link
You obviously have a hatred for Intel, and I think it's clouding your judgment. I have no particular love for Intel. I think the company has become a corporate boondoggle and is wasting a lot of money. But I also see people that seen to resent Intel just because they are big and successful, and those people say things that confirm their biases and wishes without fully considering the situations. As an example, in the other article, where people conveniently show no awareness of the differences between Intel's position and TSMC's that can make a process successful for TSMC which would be a failure for Intel.As for what you just said, if TSMC can get their 7 nm to work OK without EUV then why can't Intel get their 10 nm to work? They just needed more time. From what I've seen, insertion of EUV in a process is a big deal and it demands a major redesign. Sure it's possible Intel helped their 10 nm problems by using EUV, but why wouldn't they just say that? Anyway, I've had enough of this topic. You can be sure of whatever you want.
Ex EUV guy - Wednesday, December 11, 2019 - link
If they had not decreased funding for EUV in 2005, they could have had it a year or two earlier.edzieba - Thursday, December 12, 2019 - link
"It will be interesting to see if the speed of the High-NA EXE machines will be similar or better to the NXE machines."High-NA = hayai, na?
ksec - Thursday, December 12, 2019 - link
Wanted to point out TSMC 3nm is aiming at 2022. i.e High NA EUV are likely for 2nm if not 1.4nm.name99 - Friday, December 13, 2019 - link
3nm will mean whatever TSMC wants it to mean, ie whatever is ready to roll out in 2022.This MAY be smaller lithography (driven by high NA).
OR it may mean GAA transistors at 5nm lithography.
OR it may mean new materials
OR...
That's why TSMC is king: because they're testing multiple things simultaneously, but they only move the non-risky ones into production, AND they don't shoot their mouths off about what they'll be doing ten years from now, so they have no particular stake in what "defines" the 3nm node. 3nm will be exactly what I said -- all the stuff that's ready to roll in 2022, none of the stuff that isn't.
ballsystemlord - Friday, February 7, 2020 - link
Spelling error:"...whcih take about 10% of that downtime:..."
which is misspelled:
"...which take about 10% of that downtime:..."