ARM Announces 10FF "Artemis" Test Chipby Andrei Frumusanu on May 18, 2016 10:00 AM EST
Today in collaboration with TSMC, ARM's physical IP division is announcing the tapeout of a 10nm test chip demonstrating the company's readiness for the new manufacturing process. The new test chip is particularly interesting as it contains ARM's yet-to-be-announced "Artemis" CPU core. ARM discloses that tapeout actually took place back in December 2015 and is expecting silicon to come back from the foundry in the following weeks.
The test chip serves as a learning platform for both ARM and TSMC in tuning their tools and manufacturing process to achieve the best results in terms of performance, power, and area. ARM actually implemented a full 4-core Artemis cluster on the test chip which should serve as a representative implementation of what vendors are expected to use in their production designs. The test chip also harbours a current generation Mali GPU implementation with 1 shader core that serves as a demonstration of what vendors should expect when choosing ARM's POP IP in conjunction with its GPU IP. Besides the CPU and GPU we find also a range of other IP blocks and I/O interfaces that are used for validation of the new manufacturing process.
TSMC's 10FF manufacturing process primarily promises a large improvement in density with scalings of up to 2.1x compared to the previous 16nm manufacturing node. At the same time, the new process is able to achive 11-12% higher performance at each process' respective nominal voltage, or a 30% reduction in power at the same frequency.
In terms of a direct comparison between a current Cortex A72 design on 16FF+ and an Artemis core on 10FF on the preliminary test chip with an early physical design kit (PDK) we see that the new CPU and process are able to roughly halve the dynamic power consumption. Currently clock frequencies on the new design still don't reach what is achievable on the older more mature process and IP, but ARM expects this to change in the future as it continues to optimise its POP and the process stabilises.
As manufacturing processes increasingly rise in their complexity, physical design implementation becomes an increasingly important part of CPU and SoC designs. As such, tools such as ARM's POP IP become increasingly important for vendors to be able to achieve a competitive result both in terms of PPA and time-to-market of an SoC. Today's announcement serves as demonstration of ARM commitment to stay ahead of the curve in terms of enabling its partners to make the best out of the IP that they license.
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SaolDan - Wednesday, May 18, 2016 - linkNEAT!!
Shadowmaster625 - Wednesday, May 18, 2016 - linkSo in about 3 years we will see products?
ddriver - Wednesday, May 18, 2016 - linkSeems like 6 to 9 months to me
lefty2 - Wednesday, May 18, 2016 - linkThe first product will be the Apple A11 in autumn 2017.
revanchrist - Wednesday, May 18, 2016 - linkIf you meant the first 10nm Artemis SoC then it's probably MTK's Helio X30 which should be available on 1H 2017. But X30 has only two Artemis cores, so it's not really a high end product.
iwod - Wednesday, May 18, 2016 - link1H 2017, in small quantities and expensive, all the way until 1H 2018, in between you have Apple taking the majority of capacity.
levizx - Wednesday, August 17, 2016 - linkFunny how Apple can also take capacity from GF/Samsung/Intel whilst having no chips with them.
Eden-K121D - Wednesday, May 18, 2016 - linkwill be interesting to see how Apple A11 and Snapdragon 830 perform as they will be made on 10nm FF process
Samus - Wednesday, May 18, 2016 - linkIt always is. Apple usually goes with 2 monster cores (with lots of cache) for strong single/dual threaded performance and others usually go for weaker quad or octa configs at higher frequencies and less cache per core. The optimization of iOS for single threaded performance often helps Apple boost performance too.
Sunamer - Wednesday, May 18, 2016 - link"The optimization of iOS for single threaded performance often helps Apple boost performance too."
iOS is not single-thread optimized. Where did you get that from?