Every decade is the decade that tests the limits of Moore’s Law, and this decade is no different. With the arrival of Extreme Ultra Violet (EUV) technology, the intricacies of multipatterning techniques developed on previous technology nodes can now be applied with the finer resolution that EUV provides. That, along with other more technical improvements, can lead to a decrease in transistor size, enabling the future of semiconductors. To that end, Today IBM is announcing it has created the world’s first 2 nanometer node chip.

Names for Nodes

Just to clarify here, while the process node is being called ‘2 nanometer’, nothing about transistor dimensions resembles a traditional expectation of what 2nm might be. In the past, the dimension used to be an equivalent metric for 2D feature size on the chip, such as 90nm, 65nm, and 40nm. However with the advent of 3D transistor design with FinFETs and others, the process node name is now an interpretation of an ‘equivalent 2D transistor’ design.

Some of the features on this chip are likely to be low single digits in actual nanometers, such as transistor fin leakage protection layers, but it’s important to note the disconnect in how process nodes are currently named. Often the argument pivots to transistor density as a more accurate metric, and this is something that IBM is sharing with us.

Transistor Density

Today’s announcement states that IBM’s 2nm development will improve performance by 45% at the same power, or 75% energy at the same performance, compared to modern 7nm processors. IBM is keen to point out that it was the first research institution to demonstrate 7nm in 2015 and 5nm in 2017, the latter of which upgraded from FinFETs to nanosheet technologies that allow for a greater customization of the voltage characteristics of individual transistors.

IBM states that the technology can fit ’50 billion transistors onto a chip the size of a fingernail’. We reached out to IBM to ask for clarification on what the size of a fingernail was, given that internally we were coming up with numbers from 50 square millimeters to 250 square millimeters. IBM’s press relations stated that a fingernail in this context is 150 square millimeters. That puts IBM’s transistor density at 333 million transistors per square millimeter (MTr/mm2).

For comparison:

Peak Quoted Transistor Densities (MTr/mm2)
AnandTech IBM TSMC Intel Samsung
22nm     16.50  
16nm/14nm   28.88 44.67 33.32
10nm   52.51 100.76 51.82
7nm   91.20 237.18* 95.08
5nm   171.30    
3nm   292.21*    
2nm 333.33      
Data from Wikichip, Different Fabs may have different counting methodologies
* Estimated Logic Density

As you can tell, different foundries have different official names with a variety of densities. It’s worth noting that these density numbers are often listed as peak densities, for transistor libraries where die area is the peak concern, rather than frequency scaling – often the fastest parts of a processor are half as dense as these numbers due to power and thermal concerns.

Stacked GAA

With regards the movement to Gate-All-Around / nanosheet transistors, while not explicitly stated by IBM, images show that this new 2nm processor is using a three-stack GAA design. Samsung is introducing GAA at 3nm, while TSMC is waiting until 2nm. Intel by contrast, we believe, will introduce some form of GAA on its 5nm process.

IBM’s 3-stack GAA uses a cell height of 75 nm, a cell width of 40 nm, and the individual nanosheets are 5nm in height, separated from each other by 5 nm. The gate poly pitch is 44nm, and the gate length is 12 nm. IBM says that its design is the first to use bottom dieletric isolation channels, which enables the 12 nm gate length, and that its inner spacers are a second generation dry process design that help enable nanosheet development. This is complimented by the first use of EUV patterning on the FEOL parts of the process, enabling EUV at all stages of the design for critical layers.

Users might be wondering why we’re hearing that IBM is the first to a 2nm chip. IBM is one of the world’s leading research centers on future semiconductor technology, and despite not having a foundry offering of their own, IBM develops IP in collaboration with others for their manufacturing facilities. IBM sold its manufacturing to GlobalFoundries with a 10 year partnership commitment back in 2014, and IBM also currently works with Samsung, and recently announced a partnership with Intel. No doubt the latter two will be partnering with IBM on some level around this new development for its viability in their own production chain.

IBM Albany Research Center

No details on the 2nm test chip have been provided, although at this stage it is likely to be a simplified SRAM test vehicle with a little logic. The 12-inch wafer images showcase a variety of different light diffractions, which likely points to a variety of test cases to affirm the viability of the technology. IBM says that the test design uses a multi-Vt scheme for high-performance and high-efficiency application demonstrations.

Wafer up close

The chip was designed and made at IBM’s Albany research facility, which features a 100,000 sq. ft. clean room. The purpose of this facility is to build on IBM’s expansive patent and licensing portfolio for collaborations with partners.

We have a set of questions with IBM’s experts awaiting response. We also now have an active invitation to go visit, as and when we can travel again.

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  • Arsenica - Thursday, May 6, 2021 - link

    Also Ian: ask them to let you bite one of the 450mm wafers they have gathering dust over there.
  • Oxford Guy - Thursday, May 6, 2021 - link

    'nothing about transistor dimensions resembles a traditional expectation of what 2nm might be.'

    Thank you for pointing this out to readers. As someone who values accuracy in terminology more than marketing emotion, it's nice to see someone state the facts rather than just the emotional appeal from marketing departments.

    Perhaps putting quotes around 2nm in the headline is a good idea.
  • WaltC - Thursday, May 6, 2021 - link

    If you know nothing about instruction capability and processing power, circuit design & complexity, then you don't know anything worth knowing about the "2nm chip." Reminds me of a university study I read years ago about this college that designed and manufactured a 1,000,000 MHz chip back when CPUs were clocking at hundreds of MHz. The catch? It did exactly one instruction per clock...;) Which actually made it fairly slow at the time. I also remember when Intel was advertising that it was using 90nm in production at a time when everyone was stuck at 130nm...;) The catch? Intel used it to manufacture ram--but CPUs @ 90nm were a year or two away. There's always a catch...;)
  • sweetgoals - Thursday, May 6, 2021 - link

    Just because you are first doesn't mean you'll be the best. Sucks to be IBM they don't have any manufacturing capability. The only money they can make off this is the licensing deals, but does Samsung or TMSC really need it? I would say not. To take any advantage IBM would need to get these designs into someone's chip software and manufacturing. So the reality is that the only thing this is good for is "Hey, look at us! We cool!" While in reality they suck.
  • iphonebestgamephone - Thursday, May 6, 2021 - link

    Probably not as much as you
  • FunBunny2 - Friday, May 7, 2021 - link

    "Sucks to be IBM they don't have any manufacturing capability."

    but... isn't that exactly the same place Apple is?

    in general, all of this discussion amounts to what Gates said upwards of 40 years ago: 'Windows is slow? let the hardware fix it.' how much of 'innovation' is different from 'widen this' and 'lengthen that'? it's all just throwing more transistors at the problem. in the political world, that's just "they're just throwing money at the problem, not fixing it." of course, if you're getting the money (transistors) you're happy. sometimes the only tool you have is a sledge.
  • Oxford Guy - Friday, May 7, 2021 - link

    In politics, fixing it means getting the fix made and in.
  • Spunjji - Friday, May 7, 2021 - link

    "The only money they can make off this is the licensing deals, but does Samsung or TMSC really need it? I would say not."

    Are you Samsung or TSMC? If not, why does it matter much what you say?
  • 0ldman79 - Thursday, May 6, 2021 - link

    Keep in mind these are peak numbers, not average or worst case.

    Frankly I don't believe there is ever a point where the transistors are as dense as Intel claims.

    Intel gave out transistor count in the past when a CPU was released, they quit doing that and I think the reason why is they're making claims that they can't back up.

    Intel's 14nm is not twice as dense as TSMC's 14nm on average. Their SRAM density is pretty close on all companies from 14nm down to 7nm and that's the densest part of the chip.

    What are they going by to say they're twice as dense as their competitors on the same process when SRAM density is generally within 20%, even across multiple lithographies?
  • Smell This - Friday, May 7, 2021 - link

    I remember that article from AT __ something like design *structural vs functional* densities? I don't recall if it incorporated transistor 'cell libraries' (but there was another article at about the same time concerning dense cell libraries on AMD Excavator __ maybe 'short cells' for uncore/graphics ?) ...

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