Every decade is the decade that tests the limits of Moore’s Law, and this decade is no different. With the arrival of Extreme Ultra Violet (EUV) technology, the intricacies of multipatterning techniques developed on previous technology nodes can now be applied with the finer resolution that EUV provides. That, along with other more technical improvements, can lead to a decrease in transistor size, enabling the future of semiconductors. To that end, Today IBM is announcing it has created the world’s first 2 nanometer node chip.

Names for Nodes

Just to clarify here, while the process node is being called ‘2 nanometer’, nothing about transistor dimensions resembles a traditional expectation of what 2nm might be. In the past, the dimension used to be an equivalent metric for 2D feature size on the chip, such as 90nm, 65nm, and 40nm. However with the advent of 3D transistor design with FinFETs and others, the process node name is now an interpretation of an ‘equivalent 2D transistor’ design.

Some of the features on this chip are likely to be low single digits in actual nanometers, such as transistor fin leakage protection layers, but it’s important to note the disconnect in how process nodes are currently named. Often the argument pivots to transistor density as a more accurate metric, and this is something that IBM is sharing with us.

Transistor Density

Today’s announcement states that IBM’s 2nm development will improve performance by 45% at the same power, or 75% energy at the same performance, compared to modern 7nm processors. IBM is keen to point out that it was the first research institution to demonstrate 7nm in 2015 and 5nm in 2017, the latter of which upgraded from FinFETs to nanosheet technologies that allow for a greater customization of the voltage characteristics of individual transistors.

IBM states that the technology can fit ’50 billion transistors onto a chip the size of a fingernail’. We reached out to IBM to ask for clarification on what the size of a fingernail was, given that internally we were coming up with numbers from 50 square millimeters to 250 square millimeters. IBM’s press relations stated that a fingernail in this context is 150 square millimeters. That puts IBM’s transistor density at 333 million transistors per square millimeter (MTr/mm2).

For comparison:

Peak Quoted Transistor Densities (MTr/mm2)
AnandTech IBM TSMC Intel Samsung
22nm     16.50  
16nm/14nm   28.88 44.67 33.32
10nm   52.51 100.76 51.82
7nm   91.20 237.18* 95.08
5nm   171.30    
3nm   292.21*    
2nm 333.33      
Data from Wikichip, Different Fabs may have different counting methodologies
* Estimated Logic Density

As you can tell, different foundries have different official names with a variety of densities. It’s worth noting that these density numbers are often listed as peak densities, for transistor libraries where die area is the peak concern, rather than frequency scaling – often the fastest parts of a processor are half as dense as these numbers due to power and thermal concerns.

Stacked GAA

With regards the movement to Gate-All-Around / nanosheet transistors, while not explicitly stated by IBM, images show that this new 2nm processor is using a three-stack GAA design. Samsung is introducing GAA at 3nm, while TSMC is waiting until 2nm. Intel by contrast, we believe, will introduce some form of GAA on its 5nm process.

IBM’s 3-stack GAA uses a cell height of 75 nm, a cell width of 40 nm, and the individual nanosheets are 5nm in height, separated from each other by 5 nm. The gate poly pitch is 44nm, and the gate length is 12 nm. IBM says that its design is the first to use bottom dieletric isolation channels, which enables the 12 nm gate length, and that its inner spacers are a second generation dry process design that help enable nanosheet development. This is complimented by the first use of EUV patterning on the FEOL parts of the process, enabling EUV at all stages of the design for critical layers.

Users might be wondering why we’re hearing that IBM is the first to a 2nm chip. IBM is one of the world’s leading research centers on future semiconductor technology, and despite not having a foundry offering of their own, IBM develops IP in collaboration with others for their manufacturing facilities. IBM sold its manufacturing to GlobalFoundries with a 10 year partnership commitment back in 2014, and IBM also currently works with Samsung, and recently announced a partnership with Intel. No doubt the latter two will be partnering with IBM on some level around this new development for its viability in their own production chain.

IBM Albany Research Center

No details on the 2nm test chip have been provided, although at this stage it is likely to be a simplified SRAM test vehicle with a little logic. The 12-inch wafer images showcase a variety of different light diffractions, which likely points to a variety of test cases to affirm the viability of the technology. IBM says that the test design uses a multi-Vt scheme for high-performance and high-efficiency application demonstrations.

Wafer up close

The chip was designed and made at IBM’s Albany research facility, which features a 100,000 sq. ft. clean room. The purpose of this facility is to build on IBM’s expansive patent and licensing portfolio for collaborations with partners.

We have a set of questions with IBM’s experts awaiting response. We also now have an active invitation to go visit, as and when we can travel again.

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  • andrewaggb - Friday, May 7, 2021 - link

    I don't see how you can say your 5900x is unstable if it's unopened.
  • Peskarik - Saturday, May 8, 2021 - link

    I did not say that. I said there is a probability given what I read in different forums. I decided to take my chances and build an AMD system now, but that's primarily because current Intel chips are way behind AMD in performance and way too hot, otherwise I would use Intel as I had good experience with them.
  • Linustechtips12#6900xt - Monday, May 10, 2021 - link

    i havent had any issues with zen3, it was one of the easist transition honestly. b450m pro 4 bios update then i jsut plopped it in and dne easy as that
  • Spunjji - Tuesday, May 18, 2021 - link

    Alas, the 75 page thread empirically proves you wrong. 🤭
  • Zingam - Thursday, May 6, 2021 - link

    If Intel is so much denser why don't they just lower their number as is common in IT industry (well, they usually up their number for a spelling change - Google Chrome 9765778).
  • Oxford Guy - Thursday, May 6, 2021 - link

    Firefox was behind Chrome's ultra-fast version number system so Mozilla suddenly inflated the version number. Now, as far as I know, Google is the #1 source of funding for Mozilla.

    Perhaps there is something to be gleaned from that anecdote.
  • michael2k - Thursday, May 6, 2021 - link

    Intel's 14nm is roughly equivalent to TSMC's 10nm, and Intel's 10nm is roughly equivalent to TSMC's 7nm. It isn't the naming that is the problem.

    The problem is that Intel 14nm shipped in 2014 with Broadwell and is still shipping in Cypress Cove in 2021!
    Intel 10nm shipped with Palm Cove in 2018, but that was discontinued and replaced by Sunny Cove, then Willow Cove, and now Golden Cove this year.

    To put that in comparison, Apple shipped the 10nm A11 in 2017, 3 years after Intel had already been shipping 14nm parts. Apple moved to 7nm in 2018, the same year Intel's first 10nm part shipped, but due to internal delays, Intel couldn't actually transition all their products to 10nm; coupled with Apple's architectural designs, resulting in the A12 being thoroughly competitive with Intel in 2018. In 2020 Apple was able to release the A14 at 5nm, and alongside more architectural changes was thoroughly trouncing Intel (see the M1)

    So changing the numbers in the name don't help Intel leapfrog any, their process is still 3 years behind. Intel 7nm is on track for a 2023 release, finally matching and beating TSMC's 2020 5nm release.

    And of course, TSMC expects to theoretically beat Intel with 3nm in 2022. That assumes no delays on anyone's part.
  • dwisehart - Thursday, May 6, 2021 - link

    TSMC did and is doing shuttle runs of their 4nm process in Mar 2021 and Aug 2021. They also have a shuttle run of their 3nm process in Aug 2021. Shuttle runs are wafers made for multiple customers who each buy a portion of run, with wafers shared among all of the customers. For the 5nm shuttle runs, it is currently taking nearly half a year to get chips back, so the 4nm and 3nm shuttle runs probably take that long or longer.

    This is all just a way of saying that TSMC 4nm and 3nm parts are in process, but these things take time to deliver.
  • mmusto - Thursday, May 6, 2021 - link

    Let me know when you're in Albany!
  • Arsenica - Thursday, May 6, 2021 - link

    Go Steamed Clams!

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