AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm
by Ian Cutress on February 1, 2018 8:45 AM ESTOver the years we have seen various attempts from AMD and Intel to try and help improve storage performance on their mainstream platforms. Because of the solid user experience benefits that solid state storage can bring, these attempts come in two forms: to make the most of a small amount of super-fast storage, or to expand the amount of super-fast storage available. Most attempts at this have been laborious, such as Intel’s caching technology that allows a SSD or 32GB of Optane Memory to act as a quick read/write cache for a rotational drive.
AMD’s latest attempt to boost the storage performance is Enmotus FuzeDrive, a collaborative piece of software that is designed to combine several storage devices into one big disk. The principle is fairly simple: take any combination of rotational hard drive, SATA SSD, NVMe SSD, and even DRAM, and this software will create a single drive that addresses them all. The software and drivers will manage what data goes where for quicker access, rather than it appearing as one big JBOD.
The obvious red flags from the press were about DRAM, which we were told will only act as a read-cache from prepared data taken from the other drives. The other flag was about if one drive in that system fails, whether all the data is lost. The answer was a likely yes, and so the risk of such a system might be in-line with a JBOD array or similar to a RAID-0, but without the predictable speedup a RAID-0 array might bring.
Predictive caching technologies to help speed up read/write access times are, on paper, a good idea. Some SSDs already do this, by having a small amount of fast SLC cache to act as a write buffer, which the controller can then move the data around to empty the cache when the drive is idle. The difference between having something like a controller manage an embedded system and a general software package in play is that the embedded system has to work for a single drive, albeit millions of units. That arrangement is going to be as defined and engineered as much as that SSD vendor wants it to be. For a software package, it has to work across a variety of environments that might be badly configured, or in situations that the software might not be able to identify properly. As the software stretches over three or four different drives, it sounds like a potential failure in the making of one of those drives decides to die.
AMD lists several benefits of FuzeDrive: no Windows reinstall required, drives can be added to the pool at any point, or removed from the pool if sufficient spare space exists. Pools with DRAM added can be configured manually if some more DRAM is needed. AMD lists that in its testing, comparing a 500 GB hard-drive to a system with a Samsung 960 Pro added to the pool, they recorded a 578% faster Adobe Premiere launch, and a 931% faster Adobe Photoshop launch.
I could see FuzeDrive being useful in two particular scenarios: If a user as a small (32-128 GB) NVMe drive and a 1TB SSD/HDD, a single pool can be made. Users with a single large drive (SATA or HDD) could use the software to add DRAM, enabling an automatic RAM disk.
Enmotus FuzeDrive will be available for Ryzen Desktop systems, and will cost $20.
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A5 - Monday, January 8, 2018 - link
Anything that is forbes.com/sites/* is not credible. You can literally go sign up for one right now if you want.And Forbes proper isn't credible on anything outside the financial industry.
iwod - Monday, January 8, 2018 - link
I mean Christ, you have financial industry reporter reporting on tech they barely understand and having reader that credit a non technical Journal pieces as creditable source and then attacking a journalist on a technical information site labelling him or her and the site as not creditable and when the journalist has a bloody Oxford PhD in the ElecChem Field.LurkingSince97 - Thursday, January 18, 2018 - link
LOL.GloFo announced LONG AGO that they were skipping the 10nm node and going straight from 14nm to 7nm. They mentioned that there would be some 14nm tweaks.
Other competitors started tweaking their 14nm / 16nm nodes and in some cases re-branded them (tsmc, IIRC rebranded a 16nm improvement as 12nm).
There is more than one feature size measurement in a process, being able to shrink a small subset of these by a little bit will allow for some increased density. Add on some other tweaks and you can lower power too. What do you call a heavily tweaked node that only shrinks a few of the feature sizes but not all? What number is half way between 14 and 10?
It doesn't really matter what they call it. Its ~ 10% faster or 10% lower power, with ~10% to 15% higher density.
The 12nm process is essentially a 14nm+, or ++. Its not a wholly new node. Fact 1: it will be incrementally deployed as a revision to the 14nm process where you start over nearly from scratch and almost the entire manufacturing pipeline is new. Fact 2: Unlike most minor tweaks, it does increase density. There is some justification in giving it a new size due to fact 2, but it is not a brand new process due to fact 1.
A truly new node takes _years_ to develop, not months. This appeared on their roadmap suddenly. Everyone and their brother (other than you) knew that they had a 14nm+ in the works -- AMD's roadmaps had "Zen+" on a GloFo "14nm+" node. Suddenly there was no more "14nm+" on AMD's roadmaps, and it was replaced with "12nm".
Significant tweaks to an existing node however,
LurkingSince97 - Thursday, January 18, 2018 - link
Ugh, I should proof-read:Fact 1: it will be incrementally deployed as a revision to the 14nm process where you start over nearly from scratch and almost the entire manufacturing pipeline is new.
Should say:
Fact 1: it will be incrementally deployed as an upgrade to the 14nm process (many of the manufacturing steps remain identical), while an entirely new node typically implies replacing almost the entire manufacturing pipeline.
Sane Indian - Monday, January 8, 2018 - link
"Acer will use the pre-announced higher-end APUs, the Ryzen 7 2700U and Ryzen 5 2500U, but will also be pairing this with a Radeon RX 560 graphics chip."Does iGPU and dGPU can crossfire or they just independently (switch from iGPU to dGPU and vice versa) depending upon power situation.
Ian Cutress - Monday, January 8, 2018 - link
Literally the rest of the paragraph answers the question.We were told by AMD that the integrated graphics and discrete graphics will be used in a switching context: for video playback, the lower power integrated graphics is used and the discrete is disabled, however the discrete graphics is fired up for gaming work. For compute, or for games that support multi-adaptor DirectX 12 technologies, both the integrated graphics and the discrete graphics should be available, however this is up to the game/software to implement.
Kevin G - Monday, January 8, 2018 - link
AMD executing right now and while there is argument that they've played it safe with Zen so far, they are in a very favorable position in the market. -"While most of the roadmap could have been predicted by those of us embedded in this industry, it was good to see AMD volunteering a lot of information. This can be a bit of a double-edged sword, if a competitor knows what you have planned". AMD knows that Intel's roadmap is in chaos as right now and pushing existing Zen designs to lower power envelopes and/or increasing clock speeds will close the performance gap. If Zen 2 advances in terms of IPC by any significant margin, they could actually pull ahead in 2019 but that entirely depends on Intel's response, in particular Ice Lake.Intel's missteps with 10 nm has left them open as the first Cannon Lake parts were due in late 2016! Meltdown and Spectre meltdown could have been the death blow to Cannon Lake as the incoming lawsuits make it unwise to release products with such significant flaws. Intel's server line up is also in chaos due to Meltdown/Spectre as Cascade Lake was pinned in as a stop-gap 14 nm solution before Cannon Lake-SP in 2019. Cascade lake for release this year should already be sampling but Meltdown/Spectre could force a delay. In particular is that Cascade Lake is supposed to support Optane DIMMs. The 10 nm Knight's Hill HPC processor has been cancelled roughly a month ago and replaced by Knight's Mill as a stop-gap for partners looking into AI. We'll probably find out later today when Intel's CEO takes the stage at CES.
wumpus - Monday, January 8, 2018 - link
"Death blow"? You seem to vastly overestimate the amount of silicon GoFlo can produce. Even if everything goes right for AMD, Intel will be shipping Cannon Lake chips left and right to consumers (the chips in the article appeared mostly for consumers) as GoFlo furiously produces Zepplin (or whatever its followup is called) and AMD ships them as hyperprofitable EPYC chips.That said, Intel certainly takes AMD competition seriously enough to throw together competing products such as the X299, even if such products make the rest of Intel look like they have no idea what they are doing. But still, massive gains for AMD will look like a tiny blip in Intel's revenue.
Orenj - Monday, January 8, 2018 - link
With Zen 2 already complete, I'm wondering if it contains any hardware assists for mitigation of Spectre-type attacks a la Intel's proposed IBRS/STIBP/IBPB?PixyMisa - Monday, January 8, 2018 - link
Unlikely; they've only known about this for a couple of months.