Intel's Optimized Turbo Profiles

Also new to Skylake-SP, Intel has also further enhanced turbo boosting.

There are also some security and virtualization enhancements (MBE, PPK, MPX) , but these are beyond the scope this article as we don't test them. 

Summing It All Up: How Skylake-SP and Zen Compare

The table below shows you the differences in a nutshell.

  AMD EPYC 7000
 
Intel Skylake-SP Intel Broadwell-EP
 
Package & Dies Four dies in one MCM Monolithic  Monolithic
Die size 4x 195 mm² 677 mm² 456 mm²
On-Chip Topology Infinity Fabric
(1-Hop Max)
Mesh Dual Ring
Socket configuration 1-2S 1-8S ("Platinum") 1-2S
Interconnect (Max.)
Bandwidth (*)(Max.)
4x16 (64) PCIe lanes
4x 37.9 GB/s
3x UPI 20 lanes
3x 41.6 GB/s
2x QPI 20 lanes
2x 38.4 GB/s
TDP 120-180W 70-205W 55-145W
8-32 4-28 4-22
LLC (max.) 64MB (8x8 MB) 38.5 MB 55 MB
Max. Memory 2 TB 1.5 TB 1.5 TB
Memory subsystem
Fastest sup. DRAM
8 channels
DDR4-2666
6 channels
DDR4-2666
4 channels
DDR4-2400
PCIe Per CPU in a 2P 64 PCIe (available) 48 PCIe 3.0 40 PCIe 3.0

(*) total bandwidth (bidirectional)

At a high level, I would argue that Intel has the most advanced multi-core topology, as they're capable of integrating up to 28 cores in a mesh. The mesh topology will allow Intel to add more cores in future generations while scaling consistently in most applications. The last level cache has a decent latency and can accommodate applications with a massive memory footprint. The latency difference between accessing a local L3-cache chunk and one further away is negligible on average, allowing the L3-cache to be a central storage for fast data synchronization between the L2-caches. However, the highest performing Xeons are huge, and thus expensive to manufacture. 

AMD's MCM approach is much cheaper to manufacture. Peak memory bandwidth and capacity is quite a bit higher with 4 dies and 2 memory channels per die. However, there is no central last level cache that can perform low latency data coordination between the L2-caches of the different cores (except inside one CCX). The eight 8 MB L3-caches acts like - relatively low latency - spill over caches for the 32 L2-caches on one chip.  

Intel's New On-Chip Topology: A Mesh Xeon Skylake-SP SKUs
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  • JohanAnandtech - Friday, July 21, 2017 - link

    Thanks! It is was a challenge, and we will update this article later on, when better kernel support is available.
  • serendip - Tuesday, July 11, 2017 - link

    What idiot marketroid thought it was cool to have a huge list of SKUs and gimped "precious metals" branding? I'd like to see Epyc kicking Xeon butt simply because AMD has much more sensible product lists and there's not much gimping going on.
  • ParanoidFactoid - Tuesday, July 11, 2017 - link

    Reading through this, the takeaway seems thus. Epyc has latency concerns in communicating between CCX blocks, though this is true of all NUMA systems. If your application is latency sensitive, you either want a kernel that can dynamically migrate threads to keep them close to their memory channel - with an exposed API so applications can request migration. (Linux could easily do this, good luck convincing MS). OR, you take the hit. OR, you buy a monolithic die Intel solution for much more capital outlay. Further, the takeaway on Intel is, they have the better technology. But their market segmentation strategy is so confusing, and so limiting, it's near impossible to determine best cost/performance for your application. So you wind up spending more than expected anyway. AMD is much more open and clear about what they can and can't do. Intel expects to make their money by obfuscating as part of their marketing strategy. Finally, Intel can go 8 socket, so if you need that - say, high core low latency securities trading - they're the only game in town. Sun, Silicon Graphics, and IBM have all ceded that market.
  • msroadkill612 - Wednesday, July 12, 2017 - link

    "it's near impossible to determine best cost/performance for your application. So you wind up spending more than expected anyway. AMD is much more open and clear about what they can and can't do. Intel expects to make their money by obfuscating as part of their marketing strategy.

    Finally, Intel can go 8 socket, so if you need that - say, high core low latency securities trading - they're the only game in town. Sun, Silicon Graphics, and IBM have all ceded that market."

    & given time is money, & intelwastes customers time, then intel is expensive.

    Those guys will go intel anyway, but just sayin, there is already talk of a 48 core zen cpu, making 98 cores on a mere 2p mobo.

    As i have posted b4, if wall street starts liking gpu compute for prompter answers, amdS monster apuS will be unanswerable.
  • nils_ - Wednesday, July 19, 2017 - link

    98 cores on a 2p mobo isn't quite right if you keep in mind that the 32 core versions already constitute a 4 CPU system, unless AMD somehow manages to get more cores on a single die.
  • nils_ - Wednesday, July 19, 2017 - link

    Good analysis, although Sun and IBM are still coming out with new CPUs and at least with IBM there is renewed interest in the POWER ecosystem.
  • eek2121 - Wednesday, July 12, 2017 - link

    , but rather AMD's spanking new EPYC server CPU. Both CPUs are without a doubt very different: micro architecture, ISA extentions, <snip>

    Should be extensions.
  • intelemployee2012 - Wednesday, July 12, 2017 - link

    After looking at the number of people who really do not fully understand the entire architecture and workloads and thinking that AMD Naples is superior because it has more cores, pci lanes etc is surprising.
    AMD made a 32 core server by gluing four 8core desktop dies whereas Intel has a single die balanced datacenter specific architecture which offers more perf if you make the entire Rack comparison. It's not the no of cores its the entire Rack which matters.
    Intel cores are superior than AMD so a 28 core xeon is equal to ~40 cores if you compare again Ryzen core so this whole 28core vs 32core is a marketing trick. Everyone thinks Intel is expensive but if you go by performance per dollar Intel has a cheaper option at every price point to match Naples without compromising perf/dollar.
    To be honest with so many Fabs, don't you think Intel is capable of gluing desktop dies to create a 32core,64core or evn 128core server (if it wants to) if thats the implementation style it needs to adopt like AMD?
    The problem these days is layman looks at just numbers but that's not how you compare.
  • sharath.naik - Wednesday, July 12, 2017 - link

    Agree, Most who look at these numbers will walk away thinking AMD is doing well with EPYC. The article points out the approach to testing and also states the performance challenges with EPYC, which can be missed who reading this review without the prior review on the older Xeons. For example the Big data test, I bet the newbies will walk away thinking EPYC beats the older XEONS E5 v4, as thats what the graphs show,without ever looking back at the numbers for a single 22 core Xeon e5 v4. So yes, a few back links in the article will be helpful.
  • warreo - Wednesday, July 12, 2017 - link

    Not a fanboi of either company, but care to elaborate more? I checked the original Xeon E5 v4 review. It shows that a single Xeon E5 v4 performs about 10% slower than a dual setup. Extrapolating that here, that means the single Xeon E5 v4 setup would be right around 4.5 jobs per day, which would make it roughly 50% slower than the dual Epyc and Xeon 8176.

    Sure, you could argue perf/dollar is better against a dual Epyc setup...but one could make the same argument against Intel's Skylake Xeons? I also wouldn't expect the performance to scale linearly anyway. Please let me know what I'm missing.

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