A quick news piece on information coming out of Intel’s annual Investor Day in California. As confirmed to Ashraf Eassa by Intel at the event, Intel’s 8th Generation Core microarchitecture will remain on the 14nm node. This is an interesting development with the recent launch of Intel’s 7th Generation Core products being touted as the ‘optimization’ behind the new ‘Process-Architecture-Optimization’ three-stage cadence that had replaced the old ‘tick-tock’ cadence. With Intel stringing out 14nm (or at least, an improved variant of 14nm as we’ve seen on 7th Gen) for another generation, it makes us wonder where exactly Intel can promise future performance or efficiency gains on the design unless they start implementing microarchitecture changes.

Despite this, if you were to believe supposed ‘leaked’ roadmaps (which we haven’t confirmed from a second source as of yet), the 8th Generation product ‘Cannon Lake’ is more geared towards the Y and U part of Intel’s roadmap. This would ring true with a mobile first strategy that Intel has mirrored with recent generations such that the smaller, low power chips are off the production line for a new product first, however we'd also expect 10nm to also be in the smaller chips first too (as demonstrated at CES). Where Cannon Lake will end up in the desktop or enterprise segment however remains to be seen. To put something a bit more solid into this, Ashraf also mentioned words from Dr. Venkata ‘Murthy’ Renduchintala, VP and GM of Client and IoT:

‘Murthy referred to it at the event, process tech use will be ‘fluid’ based on segment’.

If one read too much into this, we may start seeing a blend of process nodes for different segments at the same time for different areas of the market. We already do have that to some extent with the mainstream CPUs and the HEDT/Xeon families, but this phrasing seems that we might get another split between consumer products or consumer and enterprise. We may get to a point where Intel's 'Gen' naming scheme for its CPUs covers two or more process node variants.

Speaking of the Enterprise segment, another bit of information has also surfaced, coming from a slide during a talk by Diane Bryant (EVP/GM of Data Center) and posted online by Ashraf. The slide contains the words ‘Data center first for next process node’

We can either talk about process node in terms of the ‘number’, either 14nm/10nm/7nm, or by variants within that process (high power, high efficiency). One might suspect that this means Intel is moving hard and fast with 10nm for Xeons and big computing projects, despite showing off 10nm silicon at CES earlier this year. That being said, it’s important to remember that the data center market is large, and includes high-density systems with many cores, such as Atom cores, and Intel did recently open up its 10nm foundry business to ARM Artisan IP projects. So while the slide does say ‘Data center first’, it might be referring to DC projects based on ARM IP in that segment rather than big 4-24+ core Xeons. At this stage of the game it is hard to tell.

On top of all this, Intel still has extreme confidence in its foundry business. An image posted by Dick James of Siliconics from the livestream shows Intel expects to have a three-year process node advantage when its competitors (Samsung, TSMC) start launching 10nm:

I’ve been brief with this news for a reason - at this point there are a lot of balls in the air with many different ways to take this information, and the Investor Day is winding down on talks and finishing with smaller 1-on-1 meetings. We may get further clarification on this news as the day goes on.

Update 1: On speaking with Diane Bryant, the 'data center gets new nodes first' is going to be achieved by using multiple small dies on a single package. But rather than use a multi-chip package as in previous multi-core products, Intel will be using EMIB as demonstrated at ISSCC: an MCP/2.5D interposer-like design with an Embedded Multi-Die Interconnect Bridge (EMIB).

An Intel Slide from ISSCC, via PC Watch

Initially EMIB was thought of as a technology relating to Intel's acquisition of Altera and potential future embedded FPGA designs, and given the slide above and comments made at the Investor Day, it seems there are other plans for this technology too. The benefit of using multiple smaller dies over a large monolithic 600mm2 die is typically related to cost and yield, however the EMIB technology also has to be up to par and there may be a latency or compatibility trade-off.

Source: Intel, @TMFChipFool

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  • Michael Bay - Friday, February 10, 2017 - link

    Maybe in their dreams. TSMC nanometers are exactly like Samsung`s.
  • Meteor2 - Friday, February 10, 2017 - link

    TSMC are, basically, full of shit.
  • name99 - Friday, February 10, 2017 - link

    TSMC have delivered on their publicly announced roadmap every year over the past few years.
    Please tell us what they have promised (ie PUBLICLY announced, not what you read on some rumors site) and not delivered.
  • Meteor2 - Friday, February 10, 2017 - link

    It's nothing to do with their past performance. It's the fact they're claiming there's a clear route down to 3 nm, while everyone else says 7 nm is going to be a real challenge with no clear path after. Both can't be right.
  • name99 - Friday, February 10, 2017 - link

    Try to distinguish between what TSMC ACTUALLY say and what various rumors, so-called journalists, fan-boys, and straight-out nuts claim...

    Here's TSMC's official position:

    10nm in on the map, 7nm is on the map. 5nm counts as long term research with no date attached to it yet. Nothing about 3nm.

    The nearest TSMC has said to what you claim is that they are NEGOTIATING about ONE DAY buying a piece of land that will EVENTUALLY (no earlier than 2022) produce chips that will at some (perhaps later) point be 5nm and 3nm.
    That's hardly a claim of a "clear route"...
  • Meteor2 - Sunday, February 12, 2017 - link

  • Meteor2 - Sunday, February 12, 2017 - link

    "TAIPEI — Taiwan Semiconductor Manufacturing Co. (TSMC) said that it plans to build its next fab for chips made at the 5-nm to 3-nm technology node as early as 2022 as it aims for industry leadership.

    "“Taiwan’s minister of science and technology (Yang Hung-duen) met TSMC a few months ago, so we took the opportunity to present to him our future plans,” said director of corporate communications Elizabeth Sun, confirming reports in the local press citing Yang. “We wanted him to know that we need a piece of land, because the other science parks in Taiwan are pretty full.”

    "EUV Still Uncertain
    The company said that it is still undecided on whether it will adopt extreme ultraviolet (EUV) lithography for 5 nm and 3 nm.

    “Our current plan is to use EUV extensively for 5 nm,” Sun said. “That’s under the assumption that EUV can be ready.”

    The company said that it will ramp 7 nm in 2017, followed by 5 nm in 2019, to support smartphones and high-end mobile products with new features, including virtual reality and augmented reality."

    --so, their Director of Communications is claiming a path to 3 nm, while at the same time admitting that they need EUV, but it not be ready. As I said, full of shit.
  • Yojimbo - Friday, February 10, 2017 - link

    Why is TSMC's 7nm is equivalent to Intel's 10nm? That statement is in direct opposition to the reality of the current state of fabrication processes. There is very little chance they are "equivalent". If they are equivalent under some particular metric then tell us which metric you mean.
  • name99 - Friday, February 10, 2017 - link

    The claim that they are "equivalent" rests on the fact their standard cells (TSMC 7nm and Intel 10nm) have essentially the same dimensions.

    What does this actually mean? It means they have the same DIMENSIONS, not that they have the same PERFORMANCE. Obviously the details are different, from the shape of the fins to the materials used, to the quality of the design and layout algorithms.
    Is one better than the other? Depends on what you prioritize in defining "better". Certainly of the two premier CPU design teams in the world
    - Intel hits higher frequencies (and thereby higher single-threaded performance) on their process
    - Apple hits substantially better performance at low powers on TSMC's process.

    If Apple one day gets round to releasing the mythical ARM-based Mac (and so has a power budget of, say, 65W or so to play with, rather than the 12W or so of an iPad SoC [or the 130W or so of a K-class Intel CPU] we might get a more apples-to-apples comparison of just what Apple's design and TSMC's process can do with a higher power budget.
  • Yojimbo - Friday, February 10, 2017 - link

    "What does this actually mean? It means they have the same DIMENSIONS, not that they have the same PERFORMANCE."

    Yes, so therefore they are not "equivalent" because to be "equivalent" they must have the same EVERYTHING, or at least EVERYTHING THAT MATTERS.

    Even Intel didn't go so far to try to say their 14nm and TSMC's 10nm were equivalent, and you presumably do not even work in the marketing department for TSMC.

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