A quick news piece on information coming out of Intel’s annual Investor Day in California. As confirmed to Ashraf Eassa by Intel at the event, Intel’s 8th Generation Core microarchitecture will remain on the 14nm node. This is an interesting development with the recent launch of Intel’s 7th Generation Core products being touted as the ‘optimization’ behind the new ‘Process-Architecture-Optimization’ three-stage cadence that had replaced the old ‘tick-tock’ cadence. With Intel stringing out 14nm (or at least, an improved variant of 14nm as we’ve seen on 7th Gen) for another generation, it makes us wonder where exactly Intel can promise future performance or efficiency gains on the design unless they start implementing microarchitecture changes.

Despite this, if you were to believe supposed ‘leaked’ roadmaps (which we haven’t confirmed from a second source as of yet), the 8th Generation product ‘Cannon Lake’ is more geared towards the Y and U part of Intel’s roadmap. This would ring true with a mobile first strategy that Intel has mirrored with recent generations such that the smaller, low power chips are off the production line for a new product first, however we'd also expect 10nm to also be in the smaller chips first too (as demonstrated at CES). Where Cannon Lake will end up in the desktop or enterprise segment however remains to be seen. To put something a bit more solid into this, Ashraf also mentioned words from Dr. Venkata ‘Murthy’ Renduchintala, VP and GM of Client and IoT:

‘Murthy referred to it at the event, process tech use will be ‘fluid’ based on segment’.

If one read too much into this, we may start seeing a blend of process nodes for different segments at the same time for different areas of the market. We already do have that to some extent with the mainstream CPUs and the HEDT/Xeon families, but this phrasing seems that we might get another split between consumer products or consumer and enterprise. We may get to a point where Intel's 'Gen' naming scheme for its CPUs covers two or more process node variants.

Speaking of the Enterprise segment, another bit of information has also surfaced, coming from a slide during a talk by Diane Bryant (EVP/GM of Data Center) and posted online by Ashraf. The slide contains the words ‘Data center first for next process node’

We can either talk about process node in terms of the ‘number’, either 14nm/10nm/7nm, or by variants within that process (high power, high efficiency). One might suspect that this means Intel is moving hard and fast with 10nm for Xeons and big computing projects, despite showing off 10nm silicon at CES earlier this year. That being said, it’s important to remember that the data center market is large, and includes high-density systems with many cores, such as Atom cores, and Intel did recently open up its 10nm foundry business to ARM Artisan IP projects. So while the slide does say ‘Data center first’, it might be referring to DC projects based on ARM IP in that segment rather than big 4-24+ core Xeons. At this stage of the game it is hard to tell.

On top of all this, Intel still has extreme confidence in its foundry business. An image posted by Dick James of Siliconics from the livestream shows Intel expects to have a three-year process node advantage when its competitors (Samsung, TSMC) start launching 10nm:

I’ve been brief with this news for a reason - at this point there are a lot of balls in the air with many different ways to take this information, and the Investor Day is winding down on talks and finishing with smaller 1-on-1 meetings. We may get further clarification on this news as the day goes on.

Update 1: On speaking with Diane Bryant, the 'data center gets new nodes first' is going to be achieved by using multiple small dies on a single package. But rather than use a multi-chip package as in previous multi-core products, Intel will be using EMIB as demonstrated at ISSCC: an MCP/2.5D interposer-like design with an Embedded Multi-Die Interconnect Bridge (EMIB).

An Intel Slide from ISSCC, via PC Watch

Initially EMIB was thought of as a technology relating to Intel's acquisition of Altera and potential future embedded FPGA designs, and given the slide above and comments made at the Investor Day, it seems there are other plans for this technology too. The benefit of using multiple smaller dies over a large monolithic 600mm2 die is typically related to cost and yield, however the EMIB technology also has to be up to par and there may be a latency or compatibility trade-off.

Source: Intel, @TMFChipFool

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  • serendip - Friday, February 10, 2017 - link

    I'm not a PC gamer but I've got a 7-year-old Core 2 Duo laptop that still feels snappy, thanks to RAM and SSD upgrades. 10% IPC increase per generation translates to nothing much for regular users. I think Intel will need to start renting out its fabs if it only has data centers as its main market, with PC and laptop sales slowing and Intel's mobile presence being non-existent.
  • A5 - Friday, February 10, 2017 - link

    1080p sucks. You should get a new monitor and then see how happy you are with that system.
  • fanofanand - Friday, February 10, 2017 - link

    If you had used the words me, my or I any more times I might think you wrote this post just to brag about your wonderful PC.....Other than saying how incredulous you are with your system's ability to handle modern games, nothing you said had anything to do with the article. You should just copy and paste this on all the forums you can find and maybe someone will affirm for you what a great purchasing decision you made in 2010.
  • PixyMisa - Friday, February 10, 2017 - link

    They can't. The same slide showed Kaby Lake as 15% faster than Skylake. Kaby Lake has no IPC improvements over Skylake at all, and only a 5% boost in clock speeds at the high end.

    Coffee Lake appears to be just another iteration of Skylake, and clock speeds on the 6C chips will very likely be slower than current 4C, so single-threaded performance will go down.

    Coffee Lake will at least make 6C chips mainstream, but don't look for anything significant from Intel until 2020.
  • Meteor2 - Sunday, February 12, 2017 - link

    The 6C chips will just be bigger dies as process yields improve.
  • Meteor2 - Sunday, February 12, 2017 - link

    I agree whole-heartedly with your original comment. AMD is finally providing competition.
  • TheJian - Friday, February 10, 2017 - link

    How is it possible they have enjoyed a 3yr lead at 10nm when samsung is putting out a phone or tablet in a month with 10nm. Even from their own chart there wasn't a 3yr lead vs. other's 14nm. Their own chart actually shows the other guys have a lead on them at 10nm...LOL. They will likely be beaten to 7nm also. If they hadn't thrown away 12bil+ on mobile losses, they would have spent that on R&D at fabs.

    This is pretty much the same as AMD spending on consoles etc instead of CORE products like CPU/GPU (which for Intel is FABS which leads to great chips).
  • Yojimbo - Friday, February 10, 2017 - link

    Because there is no standard on what is "10nm". Their chart is based on areal transistor density, I think. They are claiming that competitors 10nm processes will have about the same density as their 14nm node. There are other metrics to consider as far as effectiveness of a process, but if their chart is right then in terms of that one metric they have a 3 year lead.
  • Mondozai - Friday, February 10, 2017 - link

    Not really.

    As 'jjj' pointed out, TSMC will be out with 7 nm by Q4 of this year and (realistically) will be shipping in volumes of next year. TSMC's 7 nm is equivalent to Intel's 10 nm. So Intel's lead is maybe half a year at best.
  • witeken - Friday, February 10, 2017 - link

    How can TSMC be on 7nm next year when they don't even have 10nm out yet?

    People are so funny: at the same time saying that Moore's Law is dead, but then believing TSMC will hop from one node to the next in a matter of a few quarters. The only high volume 7nm you're going to see from TSMC in 2018 will likely just be the iPhone, just like 20nm in 2014.

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