TSMC: 5nm on Track for Q2 2020 HVM, Will Ramp Faster Than 7nmby Anton Shilov on October 23, 2019 10:00 AM EST
TSMC’s 5 nm (N5) manufacturing technology is projected to provide significant benefits when it comes to performance, power, and area scaling, which is why the contract maker of semiconductors expects a tangible number of its customers to adopt this process. And, with a forecast for aggressive demand paired with some early preparation in installing new equipment, TSMC believes that its N5 technology will ramp even quicker than its 7 nm (N7) process.
In a bid to boost its production capacities, TSMC recently increased its capital expenditures for 2019 from $10 billion - $11 billion to $14 billion - $15 billion. TSMC is particularly invested in buying equipment for its cutting-edge nodes, such as ASML’s Twinscan NXE step-and-scan systems for processes that use extreme ultraviolet lithography (EUVL) for select layers. At present, TSMC’s Fab 15 is making SoCs using N7+, whereas its Fab 18 (the first phase of equipment move-in was completed in March 2019) is on-track to produce N5 chips in high volume starting Q2 2020.
The new tools that will be bought in the coming months are expected to be installed in 2020 and this is when the company will be able to quickly ramp production of chips using its N7, N7+, N7P, N6, N5, and N5P process technologies. The company is confident that it will have a very high market share with its 5 nm nodes.
C.C. Wei, vice chairman and CEO of TSMC, said the following:
First, the 5 nm ramp for next year. Certainly, as compared with six months ago, we are right now more aggressive and more optimistic about it. Hopefully, because we spend big money [...] that it will ramp up much in terms of revenue, be much faster than 7 nm. […] With that money, we spend to buy the tools to prepare everything. We do expect that our growth will go beyond 5% to 10%.
The key difference between N5 and its predecessors that use EUVL is that it is designed to use EUVL on up to 14 layers (up from four and five in case of N7+ and N6). So the ramp of N5 will increase usage of the latest equipment, and to some degree will demonstrate whether EUV tools and ecosystem is ready for prime time or not. Right now, TSMC seems to be very optimistic about EUVL. The light sources it uses offer output power of more than 250 Watts and reach target goals for availability. The company also produces its own pellicles and takes into account characteristics of currently available photoresists.
Mr. Wei said the following:
“We produce our own pellicle. We have a large number of masking capacity and everything. So even photoresist, those kind of things, we have been taking into account. We are in a high-volume production [with] EUV lithography technology. For next year, you have big — even higher volume, and I can assure you that we are all prepared.”
- TSMC’s 5nm EUV Making Progress: PDK, DRM, EDA Tools, 3rd Party IP Ready
- TSMC: First 7nm EUV Chips Taped Out, 5nm Risk Production in Q2 2019
- TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019
- TSMC Announces Performance-Enhanced 7nm & 5nm Process Technologies
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alufan - Wednesday, October 23, 2019 - linkalong with a lot of hot air, yet again intel fanbois are feeling the pinch? 7nm+ is in large scale production runs and I quote
"7nm EUV (7nm+) is in high volume production, with 15-20 percent density improvement compared with 7nm and “improved” power consumption (no figures given) compared with 7nm. Even if companies like AMD move to 7nm+, it wouldn’t be surprising if they choose to use the potential density improvements in other ways. When AMD moved to 12nm from 14nm at GF, for example, it didn’t actually change the size of its CPU design — it used the density improvement to provide additional space between features to boost clocks."
they are now risk producing 5nm cant wait for the next major Ryzen upgrade
FreckledTrout - Wednesday, October 23, 2019 - linkOf course they are marketing but then there has been a lot negative BS rumors so they likely felt inclined. Your 2021 timeframe sounds about right to me. It's what AMD thinks as well since you have Zen3 summer of 2020 on 7nm+ then Zen4 likely mid 2021 which one would assume is 5nm but then that is not known yet.
29a - Wednesday, October 23, 2019 - linkThe article says the make their own pellicles.
ksec - Wednesday, October 23, 2019 - linkDid you actually read the article? And even though N7+ was not used in A13, it is still HVM for Kirin.
Targon - Thursday, October 24, 2019 - linkTSMC is already at risk production on 5nm at this point. 2020 will have AMD on 7nm+, so by the time AMD switches to 5nm in 2021, 5nm will be mature enough for good yields on that node.
EUV is more of a tool for the fab process than some magic thing that makes things better. EUV is needed to continue to progress. Think of it in the way people love to talk about RAM latency figures while they ignore that the overall performance is what people care about, and adjusting/improving latency should be more for those who want to fine tune performance but isn't some magical thing that matters the most.
Anymoore - Friday, October 25, 2019 - linkCertainly, if they ramp 5nm they have to drop 6nm and 7nm+ as they need all of their 10~20 tools for the many EUV layers. They offered all three EUV options because it is a hard sell.
twotwotwo - Wednesday, October 23, 2019 - linkSeems possible the next nodes come quicker than the current set did across all foundries? The common ingredient seems to be "more EUV." Obviously it's been a super long/expensive road to get the first commercially workable EUV sources, get the tools' uptimes high, etc. But once you're over that initial hump, doing it on more layers etc. may not be the hard part.