Intel’s Silvermont Architecture Revealed: Getting Serious About Mobile
by Anand Lal Shimpi on May 6, 2013 1:00 PM EST- Posted in
- CPUs
- Intel
- Silvermont
- SoCs
Sensible Scaling: OoO Atom Remains Dual-Issue
The architectural progression from Apple, ARM and Qualcomm have all been towards wider, out-of-order cores, to varying degrees. With Swift and Krait, Apple and Qualcomm both went wider. From Cortex A8 to A9 ARM went OoO and then from A9 to A15 ARM introduced a significantly wider architecture. Intel bucks the trend a bit by keeping the overall machine width unchanged with Silvermont. This is still a 2-wide architecture.
At the risk of oversimplifying the decision here, Intel had to weigh die area, power consumption as well as the risk of making Atom too good when it made the decision to keep Silvermont’s design width the same as Bonnell. A wider front end would require a wider execution engine, and Intel believed it didn’t need to go that far (yet) in order to deliver really good performance.
Keeping in mind that Intel’s Bonnell core is already faster than ARM’s Cortex A9 and Qualcomm’s Krait 200, if Intel could get significant gains out of Silvermont without going wider - why not? And that’s exactly what’s happened here.
If I had to describe Intel’s design philosophy with Silvermont it would be sensible scaling. We’ve seen this from Apple with Swift, and from Qualcomm with the Krait 200 to Krait 300 transition. Remember the design rule put in place back with the original Atom: for every 2% increase in performance, the Atom architects could at most increase power by 1%. In other words, performance can go up, but performance per watt cannot go down. Silvermont maintains that design philosophy, and I think I have some idea of how.
Previous versions of Atom used Hyper Threading to get good utilization of execution resources. Hyper Threading had a power penalty associated with it, but the performance uplift was enough to justify it. At 22nm, Intel had enough die area (thanks to transistor scaling) to just add in more cores rather than rely on HT for better threaded performance so Hyper Threading was out. The power savings Intel got from getting rid of Hyper Threading were then allocated to making Silvermont an out-of-order design, which in turn helped drive up efficient use of the execution resources without HT. It turns out that at 22nm the die area Intel would’ve spent on enabling HT was roughly the same as Silvermont’s re-order buffer and OoO logic, so there wasn’t even an area penalty for the move.
The Original Atom microarchitecture
Remaining a 2-wide architecture is a bit misleading as the combination of the x86 ISA and treating many x86 ops as single operations down the pipe made Atom physically wider than its block diagram would otherwise lead you to believe. Remember that with the first version of Atom, Intel enabled the treatment of load-op-store and load-op-execute instructions as single operations post decode. Instead of these instruction combinations decoding into multiple micro-ops, they are handled like single operations throughout the entire pipeline. This continues to be true in Silvermont, so the advantage remains (it also helps explain why Intel’s 2-wide architecture can deliver comparable IPC to ARM’s 3-wide Cortex A15).
While Silvermont still only has two x86 decoders at the front end of the pipeline, the decoders are more capable. While many x86 instructions will decode directly into a single micro-op, some more complex instructions require microcode assist and can’t go through the simple decode paths. With Silvermont, Intel beefed up the simple decoders to be able to handle more (not all) microcoded instructions.
Silvermont includes a loop stream buffer that can be used to clock gate fetch and decode logic in the event that the processor detects it’s executing the same instructions in a loop.
Execution
Silvermont’s execution core looks similar to Bonnell before it, but obviously now the design supports out-of-order execution. Silvermont’s execution units have been redesigned to be lower latency. Some FP operations are now quicker, as well as integer multiplies.
Loads can execute out of order. Don’t be fooled by the block diagram, Silvermont can issue one load and one store in parallel.
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extide - Wednesday, May 8, 2013 - link
What does Tegra 4 do 1.9Ghz in?Wilco1 - Wednesday, May 8, 2013 - link
Rumour is that it goes in the next ZTE phone out in a few months.phoenix_rizzen - Tuesday, May 7, 2013 - link
Note: Tegra 4i does *not* use Cortex-A15 CPUs, it uses Cortex-A9 CPUs! In fact, there's very little "Tegra 4" in the "Tegra 4i" other than the name.lmcd - Monday, May 13, 2013 - link
And the GPU is closer to the 4 than 3.And the process node. Oh yeah, that.
name99 - Monday, May 6, 2013 - link
You're willfully missing the point (and I say that as someone who's not convinced it will be easy for Intel to get ahead).What is the value of high speed CPUs in a phone (or for that matter a tablet, or a desktop machine)? For most users it is NOT that it allows some long computation to take a shorter time; rather it's that it provides snappiness --- it allows something that would have taken 1/40th of a sec to take 1/60th of a sec, or that would have taken 1/3rd of a sec to take 1/4 of a sec.
In this world, where snappiness is what matters, the ability to run your CPU at very high speeds for very short bursts of time (as long as this does not cost you long-run power) is an exceedingly valuable asset. You're being very stupid to dismiss it.
dig23 - Thursday, May 9, 2013 - link
I think so too. This article sounds totally biased :(bkiserx7 - Monday, May 6, 2013 - link
I wish they would go all out and lay it all on the table. I think it would drive great competition through the industry.Gigaplex - Tuesday, May 7, 2013 - link
Agreed. And if it does come out "too good", just downclock it and get even better battery life.jamesb2147 - Monday, May 6, 2013 - link
This is, by far, the worst article I've ever read on Anandtech. I'm pulling you out of my RSS feed specifically because of this article.Post when you have specs, guys, not Intel slides. I don't want to see the word "should."
Homeles - Monday, May 6, 2013 - link
AnandTech's architectural analyses are some of the best in the industry. It's your loss.