Counting Transistors: Why 1.16B and 995M Are Both Correct
by Anand Lal Shimpi on September 15, 2011 12:16 PM EST- Posted in
- CPUs
- Intel
- Sandy Bridge
- Ivy Bridge
- IDF 2011
- Trade Shows
Yesterday we published Ivy Bridge's transistor count as 1.48 billion. It turns out that was wrong as Intel's Mooly Eden accidentally read the B in billion as an 8 while on stage. The real number is 1.4 billion. When we published that story we compared it to Intel's Sandy Bridge, which at launch was said to be 995 million transistors. However at IDF Intel had been using another number: 1.16 billion transistors. It turns out both are right, but why is there a difference?
When designing a microprocessor you end up with a schematic of all of the circuits and transistors in the design. With the design schematic done layout is next on the list. However sometimes in the process of moving from the schematic to layout phase, transistor count baloons. The reason is simple. There are some circuits which may be represented by a single transistor at the schematic phase, but for more efficient layout use four transistors in tandem. For Sandy Bridge the 995M number is for the number of transistors in the schematic, while 1.16 billion is how many transistors are put down at the fab. Both are correct, but the 1.16B number is directly comparable to Ivy Bridge's 1.4B transistors.
That puts Ivy Bridge's transistor count at 20.7% higher than Sandy Bridge, which is more in line with what to expect from a tick.
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Arnulf - Friday, September 16, 2011 - link
Dude, are you st00pid or something ? Just because manufacturer's production process moves to a new node this doesn't imply that they ABSOLUTELY MUST double the number of transistors in their circuit just for the sake of moving from one node to another.Anand Lal Shimpi - Sunday, September 18, 2011 - link
Sorry for the late response on this, but it's actually quite simple. The rule of thumb is to either introduce a new architecture or a new process, never both. The risk in jumping to a new process node is very high. Yields start out very low, there are bound to be issues that you didn't plan on and you have very little existing experience (other than test chips) on the process. Note that these problems only increase with larger chips, they don't get any easier.The risk in moving to a new architecture is just as big. There are a ton of unknowns. Even just increasing the size of a chip on a brand new process is super risky as I mentioned above.
This is where tick-tock comes from. You introduce a new process on a relatively unchanged design, or you introduce a new design on an existing process. The reason we don't get a huge increase in transistor count on IVB is because Intel is trying to play it safe as this is its first 22nm chip.
There are also economic factors. The first 22nm wafers will be more expensive to produce than their 32nm counterparts, so you often have to build a smaller chip in order to maintain profit margins - at least initially.
I hope this helps!
Take care,
Anand
mlkmade - Thursday, September 15, 2011 - link
I look forward to getting the juice and details of the upcoming uARCHs and all the crazy new stuff intel is cooking up for their chips...Where is all the SB-E info? where is an IVY-B onstage crazy demo?where all the uARCH details of the new chips? This IDF we get a solar powered demo and a bunch of Thunderbolt products...so boring ZZZZZZZ
ssj4Gogeta - Thursday, September 15, 2011 - link
For some reason I don't see articles listed on the homepage. You can find the IDF articles here:http://www.anandtech.com/pipeline/