Overclocking Intel's New 45nm QX9650: The Rules Have Changed

Intel Processor Power Delivery Guidelines

If you've ever overclocked a system, chances are that at some point or another you've had opportunity to become upset with your Vdroop "problem." Some users, confused as to why their system refuses to exactly match actual processor supply voltage to the value specified in BIOS, are quick to blame the quality their motherboard; still others find fault with the difference noted between their board's idle and full-load processor supply voltages. Actually, load line droop (Vdroop) is an inherent part of any Intel power delivery design specification and serves an important role in maintaining system stability. In most cases, comments regarding unacceptable power delivery performance are completely unfounded. To make matters worse, unjustified negative consumer perception surrounding this often misunderstood design feature eventually forced a few motherboard manufacturers to respond to enthusiasts' demands for action by adding an option in their BIOS that effectively disables this important function.

Based on the currently running tasks, processor load can vary significantly during system operation. The voltage regulator module (VRM) circuit closely regulates CPU supply voltage by sensing instantaneous changes in processor loading and then responds by varying the individual on-time for a bank of power MOSFETs used to charge a multi-phased LC network. This LC network is responsible for providing all of the power demanded by the processor. If the VRM senses a decreasing supply voltage, it provides more current; the opposite is true in the case where voltage is rising. This cycle of sense-and-correct, known as negative feedback, can occur at that rate of thousands to millions of times per second, depending on the particular circuit's switching frequency.

Just like CPU power, CPU supply current increases quickly at higher frequencies

During periods of high CPU demand, the VRM circuit works hard to supply the current required by the processor. However, as soon as that load is gone, the VRM circuit must act quickly in order to reduce the current supply to the level needed to match the new demand. Because it's impossible for the VRM circuit to respond instantaneously, the larger the load change the greater the maximum potential peak overshoot voltage. Controlling the magnitude of these peak values is critical for maintaining system stability. By positioning the processor's no-load (idle) voltage level higher during periods of light loading, it's possible to sustain a larger negative voltage dip without crossing the processor's lower specified voltage limit. In addition, "drooping" the load voltage as a function of supply current allows the VRM to effectively limit the maximum positive peak overshoot voltage (experienced during a heavy to light load transient) to a value below the maximum allowable CPU voltage. This resulting control system ensures the processor supply voltage, regardless of CPU load, never violates a specified limit. The following figure should help to illustrate these concepts.

As intended, Voffset and Vdroop ensure that the supply voltage never exceeds CPU VID

The CPU VID setting establishes the absolute maximum allowable processor supply voltage experienced during transient conditions and is not the target idle voltage. We hope this statement draws attention to this important distinction, as many believe the opposite to be true - a mistake all too commonly made. Together, Vdroop and Voffset ensure that the peak CPU supply voltage seen during heavy to light loading changes remains well below the established maximum. If you determine that 1.17V, as in the case above, is not sufficient for maintaining CPU stability under load, simply increasing the CPU VID does correct the problem. Let's now examine how the system responds if we remove Voffset.

Voltage oscillations while leaving heavy load can cause problems with no Voffset

As we can see, the system exceeds maximum allowable processor voltage whenever any heavy to light load transient is significant enough to warrant one or more voltage excursions above the CPU VID value. Even worse, this all happens without the user's knowledge. Again, removing Voffset completely undermines the purpose of the VID setting - which establishes the maximum CPU voltage, not the target value.