The Cortex-A78 Micro-architecture: PPA Focused

The new Cortex-A78 had been on Arm’s roadmaps for a few years now, and we have been expecting the design to represent the smallest generational microarchitectural jump in Arm’s new Austin family. As the third iteration of Arm's Austin core designs, A78 follows the sizable 25-30% IPC improvements that Arm delivered on the Cortex-A76 and A77, which is to say that Arm has already picked a lot of the low-hanging fruit in refining their Austin core.

As the new A78 now finds itself part of a sibling pairing along side the higher performance X1 CPU, we naturally see the biggest focus of this particular microarchitecture being on improving the PPA of the design. Arm’s goals were reasonable performance improvements, balanced with reduced power usage and maintaining or reducing the area of the core.

It’s still an Arm v8.2 CPU, sharing ISA compatibility with the Cortex-A55 CPU for which it is meant to be paired with in a DynamIQ cluster. We see similar scaling possibilities here, with up to 4 cores per DSU, with an L3 cache scaling up to 4MB in Arm’s projected average target designs.

Microarchitectural improvements of the core are found throughout the design. On the front-end, the biggest change has been on the part of the branch predictor, which now is able to process up to two taken branches per cycle. Last year, the Cortex-A77 had introduced as secondary branch execution unit in the back-end, however the actual branch unit on the front-end still only resolved a single branch per cycle.

The A78 is now able to concurrently resolve two predictions per cycle, vastly increasing the throughput on this part of the core and better able to recover from branch mispredictions and resulting pipeline bubbles further downstream in the core. Arm claims their microarchitecture is very branch prediction driven so the improvements here add a lot to the generational improvements of the core. Naturally, the branch predictors themselves have also been improved in terms of their accuracy, which is an ongoing effort with every new generation.

Arm focused on a slew of different aspects of the front-end to improve power efficiency. On the part of the L1I cache, we're now seeing the company offer a 32KB implementation option for vendors, allowing customers to reduce area of the core for a small hit on performance, but with gains in efficiency. Other changes were done to some structures of the branch predictors, where the company downsized some of the low return-on-investment blocks which had a larger cost on area and power, but didn’t have an as large impact on performance.

The Mop cache on the Cortex-A78 remained the same as on the A77, housing up to 1500 already decoded macro-ops. The bandwidth from the front-end to the mid-core is the same as on the A77, with an up to 4-wide instruction decoder and fetching up to 6 instructions from the macro-op cache to the rename stage, bypassing the decoder.

In the mid-core and execution pipelines, most of the work was done in regards to improving the area and power efficiency of the design. We’re now seeing more cases of instruction fusions taking place, which helps not only performance of the core, but also power efficiency as it now uses up less resources for the same amount of work, using less energy.

The issue queues have also seen quite larger changes in their designs. Arm explains that in any OOO-core these are quite power-hungry features, and the designers have made some good power efficiency improvements in these structures, although not detailing any specifics of the changes.

Register renaming structures and register files have also been optimized for efficiency, sometimes seeing a reduction of their sizes. The register files in particular have seen a redesign in the density of the entries they’re able to house, packing in more data in the same amount of space, enabling the designers to reduce the structures’ overall size without reducing their capabilities or performance.

On the re-order-buffer side, although the capacity remains the same at 160 entries, the new A78 improves power efficiency and the density of instructions that can be packed into the buffer, increasing the instructions per unit area of the structure.

Arm has also fine-tuned the out-of-order window size of the A78, actually reducing it in comparison to the A77. The explanation here is that larger window sizes generally do not deliver a good return on investment when scaling up in size, and the goal of the A78 is to maximize efficiency. It’s to be noted that the OOO-window here not solely refers to the ROB which has remained the same size, Arm here employs different buffers, queues, and structures which enable OOO operation, and it’s likely in these blocks where we’re seeing a reduction in capacity.

On the diagram, here we see Arm slightly changing its descriptions on the dispatch stage, disclosing a dispatch bandwidth of 6 macro-ops (Mops) per cycle, whereas last year the company had described the A77 as dispatching 10 µops. The apples-to-apples comparison here is that the new A78 increases the dispatch bandwidth to 12 µops per cycle on the dispatch end, allowing for a wider execution core which houses some new capabilities.

On the integer execution side, the only big addition has been the upgrade of one of the ALUs to a more complex pipeline which now also handles multiplications, essentially doubling the integer MUL bandwidth of the core.

The rest of the execution units have seen very little to no changes this generation, and are pretty much in line with what we’ve already seen in the Cortex-A77. It’s only next year where we expect to see a bigger change in the execution units of Arm’s cores.

On the back-end of the core and the memory subsystem, we actually find some larger changes for performance improvements. The first big change is the addition of a new load AGU which complements the two-existing load/store AGUs. This doesn’t change the store operations executed per cycle, but gives the core a 50% increase in load bandwidth.

The interface bandwidth from the LD/ST queues to the L1D cache has been doubled from 16 bytes per cycle to 32 bytes per cycle, and the core’s interfaces to the L2 has also been doubled up in terms of both its read and write bandwidth.

Arm seemingly already has some of the most advanced prefetchers in the industry, and here they claim the A78 further improves the designs both in terms of their memory area coverage, accuracy and timeliness. Timeliness here refers to their quick latching on onto emerging patterns and bringing in the data into the lower caches as fast as possible. You also don’t watch the prefetchers to kick in too early or too late, such as needlessly prefetching data that’s not going to be used for some time.

Much like the L1I cache, the A78 now also offers an 32KB L1D option that gives vendors the choice to configure a smaller core setup. The L2 TLB has also been reduced from 1280 to 1024 pages – this essentially improves the power efficiency of the structure whilst still retaining enough entries to allow for complete coverage of a 4MB L3 cache, still minimizing access latency in that regard.

Overall, the Cortex-A78’s microarchitectural disclosures might sound surprising if the core were to be presented in a vacuum, as we’re seeing quite a lot of mentions of reduced structure sizes and overall compromises being made in order to maximize energy efficiency. Naturally this makes sense given that the Cortex-X1 focuses on performance…

Two New "Big" Micro-architectures: A Business Model Change The Cortex-X1 Micro-architecture: Bigger, Fatter, More Performance
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  • iphonebestgamephone - Wednesday, May 27, 2020 - link

    After seeing how much better an ipad pro runs dolphin even compared to an 865, its worth jumping.
  • Spunjji - Thursday, May 28, 2020 - link

    ...if you run Dolphin, sure. If you don't want to have all the attendant ecosystem an Apple device demands, it's not such a clear and obvious jump.
  • iphonebestgamephone - Friday, May 29, 2020 - link

    Its great as a gaming and media device. I wouldnt get an iphone though, seems to throttle too fast. Just needs a 3ds emulator as of now.
  • tkSteveFOX - Wednesday, May 27, 2020 - link

    Why? ARM cores have much better efficiency under load.
    Try gaming on an iPhone and see the battery being completely vaporized in like 2Hrs compared to 4+ on an Android device.
  • dudedud - Wednesday, May 27, 2020 - link

    Do your metrics leave out screen consumption, are normalized for battery capacity, and run the exact same settings?

    I bet they don't
  • Spunjji - Thursday, May 28, 2020 - link

    Android phones tend to have larger screens, and yeah, this very website has the normalized tests. iPhones tend to have higher maximum power draw under load (although A13 improved this dramatically from the mess that was A12).

    But really, it doesn't matter. You get what you're given with the iPhone - you can't buy one that games for more than 2 hours, so if you want to game for more than 2 hours, no amount of normalized benchmark results will help you out.
  • UNCjigga - Friday, May 29, 2020 - link

    I made the switch years ago; moving from a Moto X Pure to an iPhone 6S with Apple A9. More than 2x performance and 3x battery life. I haven't looked back. My current iPhone 11 Pro is snappier than my 7th-gen Core m3 Chromebook in some benchmarks while driving a higher-res screen, and I usually end the day with at least 30% battery still left.
  • ChrisGX - Monday, July 6, 2020 - link

    The A13 is a very fast chip. Processor speed doesn't need to be increased to be on the leading edge. On the contrary, if Apple does the straightforward thing and the thing that would differentiate the A14 it would be working almost entirely on lowering power consumption (that has recently got well out of control) and improving the energy efficiency of the SoC and particularly of the performance cores. And, that also would make sense for Apple's forthcoming desktop CPUs as well. A lot of power hungry performance cores that generate a lot of heat and that then fail to sustain performance at near peak levels won't be the way to make a compelling for desktop CPUs based on A14-like performance cores.

    Comparisons with the A13 do make a certain amount of sense insofar as the main challenge is to lower power consumption rather than push core performance again, at this point. Peak integer performance of the Lightning cores is rather similar to the best Zen 2 cores out there.

    Note: Apple has an impeccable on chip power management system but the more overly power hungry that the cores of a chip are the harder it is to hide power and thermal issues.
  • SarahKerrigan - Tuesday, May 26, 2020 - link

    Also, the "20%" for A78 is 2.6GHz A77 vs 3.0GHz A78 (so, ~7% iso-clock gain.) The 30% for X1 is already iso-clock - 3GHz A77 vs 3GHz X1.
  • yankeeDDL - Tuesday, May 26, 2020 - link

    OK, thank you. Yes, it is a bit better then. Hopefully, the X1 is only the 1st iteration in the new stretegy, and a bit conservative. Hopefully, it'll close the gap a bit more.

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