HyperLane Technology

Another new addition to the A-Series GPU is Imagination's “HyperLane” technology, which promises to vastly expand the flexibility of the architecture in terms of multi-tasking as well as security. Imagination GPUs have had virtualization abilities for some time now, and this had given them an advantage in focus areas such as automotive designs.

The new HyperLane technology is said to be an extension to virtualization, going beyond it in terms of separation of tasks executed by a single GPU.

In your usual rendering flows, there are different kinds of “master” controllers each handling the dispatching of workloads to the GPU; geometry is handled by the geometry data master, pixel processing and shading by the 3D data master, 2D operations are handled by the 2D data, master, and compute workloads are processed by the, you guessed it, the compute data master.

In each of these processing flows various blocks of the GPU are active for a given task, while other blocks remain idle.

HyperLane technology is said to be able to enable full task concurrency of the GPU hardware, with multiple data masters being able to be active simultaneously, executing work dynamically across the GPU’s hardware resources. In essence, the whole GPU becomes multi-tasking capable, receiving different task submissions from up to 8 sources (hence 8 HyperLanes).

The new feature sounded to me like a hardware based scheduler for task submissions, although when I brought up this description the Imagination spokespeople were rather dismissive of the simplification, saying that HyperLanes go far deeper into the hardware architecture, with for example each HyperLane having being able to be configured with its own virtual memory space (or also sharing arbitrary memory spaces across hyperlanes).

Splitting GPU resources can happens on a block-level concurrently with other tasks, or also be shared in the time-domain with time-slices between HyperLanes. Priority can be given to HyperLanes, such as prioritizing graphics over a possible background AI task using the remaining free resources.

The security advantages of such a technology also seem advanced, with the company use-cases such as isolation for protected content and rights management.

An interesting application of the technology is the synergy it allows between an A-Series GPU and the company’s in-house neural network accelerator IP. It would be able to share AI workloads between the two IP blocks, with the GPU for example handling the more programmable layers of a model while still taking advantage of the NNA’s efficiency for the fixed function fully connected layer processing.

Three Dozen Other Microarchitectural Improvements

The A-Series comes with other numerous microarchitectural advancements that are said to be advantageous to the GPU IP.

One such existing feature is the integration of a small dedicated CPU (which we understand to be RISC-V based) acting as a firmware processor, handling GPU management tasks that in other architectures might be still be handled by drivers on the host system CPU. The firmware processor approach is said to achieve more performant and efficient handling of various housekeeping tasks such as debugging, data logging, GPIO handling and even DVFS algorithms. In contrast as an example, DVFS for Arm Mali GPUs for example is still handled by the kernel GPU driver on the host CPUs.

An interesting new development feature that is enabled by profiling the GPU’s hardware counters through the firmware processor is creating tile heatmaps of execution resources used. This seems relatively banal, but isn’t something that’s readily available for software developers and could be extremely useful in terms of quick debugging and optimizations of 3D workloads thanks to a more visual approach.

Fixed Function Changes & Scalability PPA Projections - Significant, If Delivered
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  • Korguz - Tuesday, December 3, 2019 - link

    and your not ?? come one melgross.. some of your posts... have pro intel all over them...
  • Korguz - Tuesday, December 3, 2019 - link

    case on point : https://www.anandtech.com/show/15162/dell-intel-cp...
  • s.yu - Tuesday, December 3, 2019 - link

    Ok? Like how HiSilicon siphoned from Cambricon?
  • levizx - Tuesday, December 3, 2019 - link

    How? It's a completely different architecture.
  • vladx - Wednesday, December 4, 2019 - link

    Don't mind s.yu, he's the biggest Chinese hater on AnandTech. You would save yourself time and energy just ignoring his rambling.
  • s.yu - Wednesday, December 4, 2019 - link

    Yeah...I vaguely remember you vlad, you were singing praises for the Soviet Union and claiming that China is the best everywhere and that its government takes care of every aspect of your life from housing to employment.
    "Chinese hater"
    Yeah...common attempts of brainwashed drones to discredit me.
    FYI I am anti-Huawei+anti-Emperor Xi>anti-Party!=anti-China
    There's a big distinction there, unless you're so ignorant you could oversimplify that as equal.
  • vladx - Wednesday, December 4, 2019 - link

    Your attempts to "poison the well" are just pathetic, s.yu.
  • s.yu - Wednesday, December 4, 2019 - link

    I only see you poisoning the well with fiction. I quote multiple sources and why two other trolls scurried off after astroturfing for Huawei again.
    If you're so righteous man up and face me, lace your arguments with insults I don't care but if all you have is nothing but empty insults then that only speaks to your status as a blind drone.
  • s.yu - Wednesday, December 4, 2019 - link

    From when is it completely different, where is it different? A source would be appreciated. Now it might be different, but they're strangely forthcoming regarding the current architecture compared to past NPUs, there's not many points of reference, and Huawei doesn't deserve benefit of the doubt.
  • levizx - Tuesday, December 3, 2019 - link

    Also Cambricon is backed by Chinese Academy of Sciences - a government agency. You think they don't have any teeth to bare if Huawei stole from them?

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